Dual-Frequency CCP Etching for EUV Resist Pattern Fidelity

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Solution Overview

Problem

EUV lithography faces challenges such as lower etch selectivity, worse line edge roughness (LER) and line width roughness (LWR), and increased defectivity compared to traditional 193 nm resists, particularly at sub-30 nm technology nodes, which complicates semiconductor manufacturing.

Innovation Solution

The use of dual-frequency Capacitively Coupled Plasma (CCP) dry etching methodologies, including a repeated deposition/etch process and Direct Current Superposition (DCS) technology, to improve LER, LWR, and resist selectivity by controlling plasma parameters and applying a DC potential to electrodes, enhancing etch selectivity and pattern fidelity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If EUV lithography is used for sub-30 nm patterning, then pitch requirements are met, but etch selectivity decreases and line edge roughness worsens

Engineering Contradiction:
Improvepitch controlVSAvoidetch selectivity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent segments the patterning process into multiple steps: EUV lithography to form initial patterns, followed by selective dry etching with optimized plasma parameters to transfer patterns through multiple layers. The dual-frequency CCP etching separates the etching of different materials (resist, mandrel, spacer) into distinct process steps with tailored conditions, achieving high selectivity for each layer while maintaining sub-30 nm pitch control

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies parameter changes by using dual-frequency capacitively coupled plasma (CCP) etching with specific frequency combinations (e.g., 13.56 MHz and 27.12 MHz) to control plasma chemistry and ion energy. By adjusting gas composition (CHF3, CF4, Ar ratios), pressure, and power levels, the process achieves high etch selectivity for EUV resist and mandrel materials while maintaining smooth line edges and reducing roughness at sub-30 nm nodes

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If multiple patterning schemes are used, then pitch requirements are met, but process complexity and cost increase

Engineering Contradiction:
Improvepitch controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming a precisely patterned EUV resist layer and mandrel structure before the main etching process. The EUV lithography step creates high-resolution initial patterns that serve as templates, and the subsequent dual-frequency CCP etching transfers these patterns through multiple layers in a single controlled process, avoiding the need for multiple lithography cycles

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dual-frequency CCP etching process serves multiple functions: it etches through organic resist materials, inorganic mandrel layers, and spacer materials with appropriate selectivity in a unified process platform. This multi-functional etching approach replaces multiple specialized process steps, reducing overall process complexity while achieving sub-30 nm pitch patterns

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces LER and LWR, improves resist selectivity, and maintains resist budget, enabling more reliable pattern transfer and reduced defectivity in EUV lithography, particularly for sub-30 nm technology nodes.

Implementation Method 1

dual frequency capacitively coupled plasma (CCP)

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 2

a carbon-containing layer is deposited on the exposed portions of the coating layer

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS9818610B2Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)
Publication Date: 2017.11.14 TOKYO ELECTRON LTD
  • US9818610B2 patent drawing
  • US9818610B2 patent drawing
  • US9818610B2 patent drawing

AI summary

A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.