Dual-Fuse eFuse Circuit for Low-Resistance Read Reliability
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Solution Overview
Problem
Conventional efuse units face reliability issues due to incorrect logical output values caused by fuses not being blown or having too small resistance during programming, leading to reduced reliability and increased programming current and area requirements.
Innovation Solution
The efuse unit incorporates two fuses and three NMOS transistors, allowing for redundant programming and non-blowing operations, ensuring correct reading results by using the total resistance of both fuses, reducing programming voltage and current, and minimizing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional efuse unit uses one fuse and one NMOS control transistor, then the structure is simple, but the reliability decreases due to incorrect logical output values when the fuse is not blown or has too small resistance
Solution Approach 1:
The efuse unit is segmented into two separate fuse links (first fuse link and second fuse link) instead of using a single fuse. Each fuse link is controlled by separate NMOS transistors, allowing independent programming and reading operations. This segmentation enables redundancy where if one fuse fails to program correctly, the other can compensate, thus improving reliability while managing complexity through modular design
Solution Approach 2:
The patent implements a beforehand cushioning mechanism by using two fuse links in parallel with OR logic combination. This creates a backup system where the correct logical value can be obtained even if one fuse link fails to program properly. The redundant structure acts as a cushion against programming failures, ensuring reliability before reading operations occur
2Reliability
If conventional efuse uses high programming current to ensure fuse blowing, then programming reliability improves, but the programming current and voltage requirements increase
Solution Approach 1:
Instead of requiring complete fuse blowing through high current, the patent uses partial action by applying lower programming current that may not fully blow the fuse but creates sufficient resistance change. The OR logic combination of two fuse links ensures that even partial programming of one or both fuses produces the correct logical output, reducing the energy required while maintaining reliability
Solution Approach 2:
The patent changes the programming parameter from high current complete blowing to lower current partial resistance change. By using multiple fuse links with OR logic, the system can achieve correct logical values through smaller resistance changes in each individual fuse, thereby reducing the programming current and voltage requirements while maintaining programming reliability
3Reliability
If conventional efuse uses single fuse structure, then the area is minimized, but the area increases when adding redundant fuses for reliability
Solution Approach 1:
The patent merges two fuse links and their control circuits into a single integrated efuse unit structure. The shared components such as the sense amplifier and control logic are combined, allowing the redundant structure to achieve reliability improvement with minimal additional area overhead compared to having completely separate fuse units
Solution Approach 2:
The efuse unit structure is designed with multi-functionality where the same basic building block (fuse link with NMOS control) serves dual purposes: individual programming capability and redundant backup function. The OR logic combination allows the structure to function as both a primary programming element and a fail-safe mechanism, reducing the need for separate dedicated backup structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances programming reliability by ensuring correct reading outcomes, reduces programming voltage and current, and minimizes overall area through redundant fuse backup and non-blowing programming.
Implementation Method 1
Efuse belongs to a One-Time Programmable (OTP) memory, which is based on the principle of electromigration (EM) and achieves programming functions by blowing a fuse
Data Source
AI summary
The present invention discloses an efuse unit and an application circuit, including a first fuse, a second fuse, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor. One end of the first fuse serves as a Q1 port of the efuse unit, and the other end is connected to a drain end of the third NMOS transistor and a drain end of the first NMOS transistor. One end of the second fuse serves as a Q2 port of the efuse unit, and the other end is connected to a source end of the third NMOS transistor and a drain end of the second NMOS transistor. Gate ends of the first NMOS transistor and the second NMOS transistor are short-circuited to form a WLC port of the efuse unit. The present invention can avoid reading operation failure caused by low programming resistance of the fuse.