Dual-Gate Ferroelectric FET Back-End Integration
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Solution Overview
Problem
Conventional ferroelectric field-effect transistors (FE-FETs) cannot be formed in the back-end of integrated circuit (IC) fabrication due to the high processing temperatures required for ferroelectric materials, which exceed the thermal budget of back-end processing, limiting the integration of dual-gate FE-FET devices and occupying valuable IC space.
Innovation Solution
The formation of FE-FET devices with a top gate and bottom gate, utilizing ferroelectric materials that exhibit ferroelectric properties at temperatures within the back-end thermal budget, allowing for the integration of FE-FET devices in the back-end of ICs, which can provide 3-state or 4-state memory and increase IC density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ferroelectric materials are used in FE-FET fabrication, then ferroelectric performance is improved, but processing temperature exceeds back-end thermal budget
Solution Approach 1:
The patent changes the material parameter by using doped hafnium oxide (HfO2) instead of conventional ferroelectric materials like PZT or BTO. This material substitution allows ferroelectric properties to be achieved at lower processing temperatures (within back-end thermal budget of approximately 400°C) while maintaining comparable or improved ferroelectric performance through controlled doping and annealing processes.
2Reliability
If front-end processing is used for FE-FET fabrication, then ferroelectric performance is achieved, but valuable IC space is occupied
Solution Approach 1:
The patent moves the FE-FET fabrication process from the front-end to the back-end of IC manufacturing, effectively utilizing a different temporal dimension in the fabrication sequence. This allows the FE-FET devices to be formed after the main logic transistor layer is completed, enabling vertical integration and freeing up valuable front-end IC space for additional devices or functions.
3Quantity of substance
If dual-gate FE-FET devices are integrated, then memory density is increased, but device complexity increases
Solution Approach 1:
The patent divides the gate structure into two separate gates (top gate and bottom gate) that can be independently controlled. This segmentation allows the device to achieve multiple resistance states (3-state or 4-state memory) by combining different gate voltage polarities, thereby increasing memory density while maintaining manageable device complexity through modular structural design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of FE-FET devices in the back-end of ICs, providing increased memory density and freeing up space in the front-end for additional devices, while maintaining comparable or improved ferroelectric performance relative to front-end processed FE-FET devices.
Implementation Method 1
a first ferroelectric layer between the bottom gate electrode and the FE-FET semiconductor layer, a second ferroelectric layer between the top gate electrode and the FE-FET semiconductor layer
Data Source
AI summary
Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.