Dual-Gate Dynamic Flash Memory for Stable Erase and Data Retention
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Solution Overview
Problem
Dynamic flash memory devices face challenges in maintaining stable data retention and operation margin due to voltage fluctuations and degradation of charge carriers in floating body structures, particularly in capacitorless memory cells.
Innovation Solution
A semiconductor memory device with a semiconductor base material, impurity regions, and gate insulating and conductor layers is designed to generate a potential difference between impurity regions for memory erase operations, applying specific voltage ranges to reduce majority carriers and optimize impact ionization phenomena for writing and erasing, thereby stabilizing data retention and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If capacitorless memory cells with floating body structures are used to increase integration density, then device complexity is reduced, but voltage fluctuations and operation margin degradation occur
Solution Approach 1:
The invention divides the single floating body channel into two separate channels with two independent gate structures (first gate electrode and second gate electrode). This segmentation allows independent control of each transistor region, enabling stable operation margins while maintaining the capacitorless simple structure. The first MOS transistor region and second MOS transistor region can be controlled separately to prevent voltage fluctuations.
Solution Approach 2:
The invention introduces an insulating layer between the first gate electrode and second gate electrode, and uses this intermediate structure to isolate the two gate regions electrically. This intermediary approach allows the two gates to operate independently without interfering with each other, stabilizing the operation margin while keeping the overall device structure relatively simple.
2Loss of information
If holes are stored in the floating body channel for data retention, then data storage is achieved, but charge carrier degradation and data retention loss occur
Solution Approach 1:
By dividing the single floating body into two separate floating body regions (first MOS transistor region and second MOS transistor region), the invention isolates the charge carrier storage locations. This segmentation prevents charge carrier degradation from affecting the entire data storage system, as each region can maintain its charge carriers independently, improving data retention reliability.
Solution Approach 2:
The invention extracts the gate control function from a single unified gate structure and separates it into two independent gate electrodes. This extraction allows independent optimization of each gate's control over its respective channel, enabling better management of charge carriers and reducing degradation effects on data retention.
3Speed
If impact ionization is used for data writing in capacitorless memory, then writing speed is improved, but power consumption increases
Solution Approach 1:
The invention applies different voltage conditions to the first gate electrode and second gate electrode independently, creating localized high electric field regions only where needed for impact ionization. This local quality approach enables fast writing through impact ionization in specific regions while maintaining lower power consumption in other regions, resolving the contradiction between writing speed and power consumption.
Solution Approach 2:
The invention uses partial impact ionization by applying voltages that generate sufficient electric fields only in the necessary regions for data writing. By not excessively increasing voltage across the entire device, power consumption is controlled while still achieving adequate writing speed through localized impact ionization events in the MOS transistor regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances data retention and operation margin by stabilizing the erase operation with lower power consumption and increased reliability, preventing voltage fluctuations and charge carrier degradation, and simplifying the device structure.
Implementation Method 1
logical memory data '1' is written by retaining in a channel of an N-channel MOS transistor some or all of holes among the holes and electrons generated in the channel through an impact ionization phenomenon based on a source-drain current
Data Source
AI summary
A dynamic flash memory includes a p layer as a semiconductor base material; first and second n+ layers extending on opposite sides thereof; a first gate insulating layer partially covering the p layer; a first gate conductor layer provided thereon; a second gate insulating layer provided in contact with the first gate insulating layer and partially covering the p layer; and a second gate conductor layer provided on the second gate insulating layer and electrically isolated from the first gate conductor layer. The first and second n+ layers, and the first and second gate conductor layers are respectively connected to a source line, a bit line, a word line, and a plate line. A voltage applied to each terminal during memory erasing is always greater than or equal to 0 V such that 2 V and 0.6 V are respectively applied to the plate line and the bit line.