Dual-Gate Non-Volatile Memory Device for Multi-Bit Storage
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Solution Overview
Problem
Existing non-volatile memory devices face limitations in integration due to the short channel effect and are restricted to 1-bit operation, necessitating a dual gate structure capable of reducing short channel effects and enabling multi-bit data storage.
Innovation Solution
A dual gate structure is implemented in non-volatile memory devices, involving a silicon substrate with a silicon pin having source and drain regions, tunneling oxide film, electron trap film, and control oxide film, along with asymmetrical tunneling oxide films and work functions, allowing for multi-bit operation through controlled impurity implantation and thermal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is shrunk to increase integration, then integration density is improved, but short channel effect increases causing leakage current
Solution Approach 1:
The patent transitions from a planar 2D channel structure to a 3D vertical channel structure with dual gates positioned on opposite sides of the channel. This dimensional change allows the channel to extend vertically through multiple oxide layers, providing better gate control over the channel while maintaining reduced device footprint, thus improving integration density without suffering from short channel effects
Solution Approach 2:
The patent divides the gate structure into two separate gates positioned on opposite sides of the vertical channel, with oxide layers interspersed between the gate and channel regions. This segmentation allows independent control of each gate and provides better electrostatic control over the channel, effectively suppressing short channel effects while enabling higher integration
2Device complexity
If 1-bit operation is used, then device structure is simple, but data storage capacity is limited
Solution Approach 1:
The patent enables a single dual-gate device structure to perform multiple bit operations (2-bit, 3-bit, or 4-bit) by utilizing different read conditions (normal and reverse direction reads) and controlling different oxide layers (first oxide layer, second oxide layer, or both). This multi-functionality allows the same physical structure to store and retrieve multiple bits of data, increasing storage capacity without proportionally increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual gate structure effectively reduces short channel effects, enables multi-bit data storage, and improves integration density, facilitating higher capacity and reduced memory device size.
Implementation Method 1
growing a tunneling oxide film through an oxidization process
Implementation Method 2
sequentially growing an electron trap film for trapping electrons
Implementation Method 3
injecting an impurity or metal material
Data Source
AI summary
The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.