Nanoinformatics TRIZ Cases

Hybrid self-assembled multilayer gate dielectric increases capacitance to enable low-voltage operation for carbonaceous nanomaterial thin-film transistors.

A dielectric cut plug structure modulates the workfunction metal property of nanowire gate electrodes.

Surface modified carbon nanotubes enhance charge carrier mobility in organic semiconductors.

Vertical electrodes increase surface contact area while maintaining low electrical resistance to boost energy conversion efficiency.

Conjugated semiconducting polymers harvest light via low bandgap structures, resolving synthesis complexity and solubility trade-offs.

Replacing lithography with a carbon nanotube film mask simplifies fabrication and reduces costs while maintaining structural integrity.

Segmented dummy gate electrodes with varied etch rates prevent channel-top damage and reduce residue defects during fin formation.

Segmented drift regions in nanowire IGBTs lower on-state resistance and power loss while maintaining breakdown voltage capability.

A carbon nanotube cable structure transmits optical signals and electrical power through distinct layer configurations within a single tube.

Dihydrotetraazapentacene molecules donate electrons to carbon nanotubes via charge transfer, creating stable n-doped nano-components.

Digital etching defines the channel diameter to lower contact resistance while preserving gate dielectric integrity.

A method forms an annular semiconductor fin using a sacrificial ring structure and conformal spacer deposition to define precise gate positions.

A diode structure between emitter and collector electrodes enables large-current amplification in organic transistors.

A nonvolatile memory device incorporates an insulating buffer layer with dispersed conductive material to ensure electrical conductivity between electrodes.

A TaBNH absorbing layer with controlled boron and hydrogen content achieves low reflectivity for EUV lithography.

A carbon nanotube network apparatus operates at the percolation threshold to define predefined signal paths for efficient processing.

Titania-doped quartz glass with controlled thermal expansion prevents mold deformation, maintaining location accuracy during fine pattern transfer.

Segmenting functional zones via composite materials balances substrate adhesion against mold release, reducing pattern distortion.

A multi-bit electro-mechanical memory device unifies pull-in and FET sensing parts into a single cantilever electrode structure.

External fields order conductive nanoparticles in the floating gate to resolve contradictions between mass production capability and manufacturing precision.

Mechanically isolated position sensors detect imprint template deformation to maintain alignment precision despite thermal expansion.

Outer oxide layers on multilayer spacers prevent nitride erosion during selective silicon etching, enabling reliable nano-wire fabrication.

A nanoscale switching device uses a protective dielectric cladding layer to isolate the active region from parasitic effects.

A porphyrin copolymer containing a quinoxaline unit enables high quantum efficiency charge transfer in organic solar cells.

Radiation-curable silsesquioxane resins enable rapid UV polymerization at room temperature and low pressure.

Shadow structures on the substrate mask selected areas during deposition, preventing contamination and preserving semiconductor quality.

A dual-gate non-volatile memory structure enables multi-bit data storage through localized charge trapping.

A superlattice structure reduces interfacial electric resistance and increases rewriting cycles by minimizing energy wastage as heat.

Homogeneous nanosheet spacers prevent unintended nucleation and leakage paths during epitaxial source-drain growth.

Conjugated polymers with dithiophene units resolve solubility trade-offs to boost power conversion efficiency.

A poled superlattice structure generates electrical potential from mechanical stress using stacked semiconductor monolayers.

A translucent imprint mold transfers dual damascene patterns into organosilicon layers via photopolymerization.

Electron beam projects onto amorphous metal silicon oxide layers to form controlled metal nano particles within flash memory floating gates.

Modular lamination decouples processing steps to optimize individual organic photosensitive device components.

Automated layout generator converts FinFET designs to nanosheet structures via mandrel adjustment.

A charge collecting barrier layer prevents solvent penetration during low-temperature sintering of metal nanoparticle inks.

Placing a page register outside the three-dimensional memory stack reduces signal delays caused by longer routing paths under the array.

Reducing polishing load to 1-60 g/cm2 minimizes concave defects on glass substrates for EUVL reflective masks.

Dual composition two-dimensional transistors suppress short-channel effects below 10 nanometers while maintaining manufacturing compatibility.

Voltage-tunable phase shifter using a graphene ground electrode to modulate electromagnetic signal phase via quantum capacitance.

A semiconductor nanonet fabrication method uses chemical deoxidation followed by low-temperature annealing to strengthen inter-nanowire bonds.

Selective oxidation of silicon germanium layers creates isolation barriers in horizontal gate-all-around nanowire transistors.

Conformal source and drain metal contacts induce radial strain on a suspended fin, transferring lateral force to the channel region.

A control unit adjusts position gain ratios during imprinting to maintain stage accuracy.

A Van der Waals heterostructure stacks a semiconductor layer between metallic carbon nanotubes and graphene to create asymmetric contacts.

Magnetic contrast layers decouple defect detection from optical processing constraints, enabling reliable EUV mask inspection.

Graphene gate electrodes prevent erase saturation and enhance data retention by reducing interface defects in Al2O3 films.

Multi-region wrap-around contacts maximize surface area on stacked source-drain layers in nanosheet transistors.