Page Register Placement for 3D Memory Signal Delay Reduction
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Solution Overview
Problem
In three-dimensional non-volatile memory systems, achieving higher storage density without compromising performance is challenging due to signal delays caused by longer signal lengths and the inability to fit all control circuitry below the memory structure, leading to RC delays and inefficiencies.
Innovation Solution
The proposed solution involves arranging a page register and temporary storage devices outside the three-dimensional memory structure, with sense amplifiers and latches positioned underneath to minimize signal length and reduce delays, allowing for efficient data transfer and programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control circuitry is positioned underneath the three-dimensional memory structure, then storage density is improved, but signal delays increase due to longer signal lengths
Solution Approach 1:
The control circuitry is segmented into two parts: page registers positioned outside the three-dimensional memory structure to handle data transfer, and sense amplifiers/latches positioned underneath to minimize signal delays. This segmentation allows each component to be optimally positioned for its specific function, resolving the contradiction between storage density and signal delay.
Solution Approach 2:
Page registers act as intermediary components positioned outside the memory structure, serving as a buffer between external interfaces and the internal memory array. This intermediary positioning allows data to be staged before access, reducing the signal path length to actual memory cells while maintaining high storage density through the three-dimensional structure.
2Quantity of substance
If all control circuitry is positioned underneath the memory structure, then storage density is improved, but device complexity increases due to routing constraints
Solution Approach 1:
Control circuitry is divided into page registers (outside) and sense amplifiers (underneath), simplifying routing by placing data-handling functions outside the constrained underneath region and access functions underneath where they can efficiently interface with memory cells.
3Loss of time
If page register is positioned outside the memory structure, then signal delays are reduced, but device area increases
Solution Approach 1:
The memory structure utilizes three-dimensional stacking to achieve high density, while page registers are positioned in the two-dimensional plane outside the stack. This dimensional separation allows the critical path signals to remain short while accommodating additional circuitry without proportionally increasing the footprint of the memory array itself.
Data Source
AI summary
A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.