Stacked Source-Drain Transistor Contacts for Nanosheet Resistance

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Solution Overview

Problem

In advanced CMOS devices, the decreasing size of MOSFETs leads to increased middle-of-line (MOL) contact resistance, with the interface resistance between source/drain (S/D) contacts and S/D regions contributing significantly to total parasitic resistance, posing a challenge in achieving the required performance characteristics.

Innovation Solution

The fabrication method involves forming stacked and spaced-apart S/D regions with multi-region wrap-around contacts, utilizing alternating layers of non-sacrificial and sacrificial nanosheets, and employing a cyclic etch-back process to suppress growth on sidewalls, resulting in maximized contact area without significant parasitic capacitance introduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the size of MOSFETs is decreased to increase device density, then device density is improved, but middle-of-line contact resistance increases

Engineering Contradiction:

Improvedevice densityVSAvoidcontact resistance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The source/drain contact is divided into multiple segments (first S/D contact layer, second S/D contact layer, third S/D contact layer) that are stacked vertically and spaced apart. This segmentation allows each layer to contact different portions of the S/D region, effectively increasing the total contact area and reducing contact resistance while maintaining small device footprint.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from a conventional planar contact structure to a three-dimensional stacked contact structure. By utilizing the vertical dimension with multiple spaced-apart contact layers, the contact area is significantly increased without expanding the lateral device footprint, thereby reducing contact resistance in scaled devices.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the contact area between S/D contact and S/D region is increased to reduce contact resistance, then contact resistance is reduced, but parasitic capacitance increases

Engineering Contradiction:

Improvecontact resistanceVSAvoidparasitic capacitance

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Spacer structures are formed in the regions between the stacked S/D contact layers. These spacers provide local electrical isolation, preventing capacitance coupling between adjacent contact layers while allowing each layer to maintain its contact function. This creates different electrical properties in different local regions of the contact structure.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20210408233A1Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts

Publication Date: 2021.12.30 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.