FinFET to Nanosheet SRAM Layout Conversion
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Solution Overview
Problem
Existing SRAM layouts for FinFET and nanosheet devices require different design rules, making it challenging to convert verified FinFET SRAM layouts into nanosheet SRAM layouts without significant changes in semiconductor layers, which increases manufacturing costs and time.
Innovation Solution
A method is described that involves receiving a FinFET SRAM layout, defining mandrel exposing regions, generating mandrels and active structures, adjusting their widths based on design rule check simulations, and removing previous structures to generate a nanosheet SRAM layout, using a computer-readable storage medium with a layout generator and design rule simulator to perform these steps efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET SRAM layout is converted to nanosheet SRAM layout by changing semiconductor layers, then the layout meets nanosheet SRAM requirements, but manufacturing cost and time increase significantly
Solution Approach 1:
The patent uses a FinFET SRAM layout as a template or copy to generate the nanosheet SRAM layout through automated conversion processes. The system copies the verified design structure and transforms it according to different design rules, avoiding the need to create nanosheet layouts from scratch while ensuring compliance with nanosheet manufacturing requirements
Solution Approach 2:
The patent changes key parameters of the layout including transistor width, length, spacing, and doping concentrations to transform FinFET SRAM design into nanosheet SRAM design. By systematically adjusting these parameters according to nanosheet process requirements, the layout achieves compliance without requiring complete redesign, thus reducing manufacturing complexity
2Ease of manufacture
If FinFET SRAM layout is converted to nanosheet SRAM layout without significant changes, then manufacturing cost and time are reduced, but the layout may not meet nanosheet SRAM requirements
Solution Approach 1:
The patent implements an automated verification system that checks the converted nanosheet SRAM layout against nanosheet-specific design rules and manufacturing requirements. This feedback mechanism identifies compliance issues and triggers automatic adjustments to the layout parameters, ensuring that the final design meets all nanosheet SRAM requirements while maintaining the efficiency benefits of template-based conversion
Solution Approach 2:
The patent performs preliminary analysis of both FinFET and nanosheet design rules before conversion, identifying key parameter differences and transformation requirements in advance. This preliminary preparation enables the conversion process to make targeted adjustments rather than trial-and-error modifications, ensuring compliance is achieved efficiently
Data Source
AI summary
A method of generating a layout for a semiconductor device includes the following step. A first layout having a first well region and second well regions is received. Mandrel blocking regions is defined in the first layout. First mandrels are generated outside of the mandrel blocking regions. Active structures are generated to overlap with the first mandrels in the second well region, and a width of the active structures in the second well region is adjusted. Second mandrels are generated in the first well region on two opposite sides of the first mandrels. Active structures are generated to overlap with the second mandrel in the first well region, and a width of the active structures in the first well region is adjusted. A second layout is generated based on the active structures located in the first well region and the second well regions.