Nanowire Isolation via Selective Oxidation for hGAA Leakage Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reliably form vertically stacked nanowires with desired materials for next-generation devices, particularly for horizontal gate-all-around (hGAA) structures, where parasitic capacitance and current leakage pose significant issues, affecting device performance and isolation.
Innovation Solution
A method involving the formation of a multi-material layer with alternating pairs of silicon and Ge-containing layers on a substrate, followed by selective etching and oxidation processes, under high pressure, to create nanowire structures with controlled parasitic capacitance and leakage current, utilizing a silicon germanium oxide layer for improved isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different materials are utilized to form the channel structures (nanowires) in hGAA structures, then device performance is enhanced, but manufacturing difficulty increases and parasitic capacitance between metal gate and source/drain increases
Solution Approach 1:
The multi-material layer is divided into repeating pairs of first layers and second layers with different materials (e.g., Si and SiGe). This segmentation allows selective removal of specific layers to form suspended nanowire structures, enabling complex device architectures while maintaining manufacturing feasibility through systematic material organization
Solution Approach 2:
Different materials are strategically placed in specific locations within the multi-material layer structure. The first layers and second layers have distinct material compositions tailored for specific functions, allowing local optimization of electrical properties while managing parasitic capacitance through controlled material distribution
2Reliability
If different materials are utilized to form the channel structures (nanowires) in hGAA structures, then device performance is enhanced, but current leakage increases
Solution Approach 1:
The second layer is selectively removed from the multi-material layer through selective etching processes, creating suspended nanowire structures. This extraction removes material that would otherwise contribute to parasitic capacitance and current leakage paths, while retaining the essential functional materials in the first layers
Solution Approach 2:
The selective oxidation process acts as an intermediary mechanism that transforms the bottom structure into an oxidized layer, creating a controlled interface that manages current leakage. This intermediary transformation allows precise control over electrical properties at critical interfaces
3Reliability
If selective oxidation is performed on the bottom structure, then device isolation is improved, but process complexity increases
Solution Approach 1:
The bottom structure is prepared in advance with specific material composition (e.g., SiGe with controlled Ge ratio) before the selective oxidation process. This preliminary preparation ensures that the bottom structure is selectively oxidizable while other layers remain intact, simplifying the overall process by pre-establishing material differentiation
Solution Approach 2:
The selective oxidation process utilizes controlled parameter changes (temperature, oxygen partial pressure, time) to achieve selective oxidation of the bottom structure. By precisely controlling these parameters, the process achieves high device isolation while maintaining manageability through well-defined process conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and leakage current, enhancing device isolation and electrical performance in hGAA structures, enabling the fabrication of more reliable and efficient semiconductor devices.
Implementation Method 1
selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer
Data Source
AI summary
The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.