Dual Gate Pixel Structure for High Aperture Ratio
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Solution Overview
Problem
Conventional dual-gate pixel structures have a low aperture ratio, which is exacerbated by the need for larger storage capacitance in twisted nematic liquid crystal displays, leading to degraded luminance due to restricted pixel electrode areas.
Innovation Solution
The pixel structure incorporates a thin film transistor with a gate insulating layer extended outside the transistor, a passivation layer covering the transistor, and pixel electrodes connected through via holes, with a common voltage line overlapping the electrodes to increase storage capacitance, reducing the distance and medium layers between the electrodes, thereby increasing the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the area of the common voltage line is increased to guarantee storage capacitance, then the storage capacitance is improved, but the aperture ratio is degraded
Solution Approach 1:
The patent transitions from a conventional single-layer capacitor structure to a multi-layer stacked capacitor structure. The first capacitor is formed between the common voltage line and the first pixel electrode in the first substrate, while the second capacitor is formed between the common voltage line and the second pixel electrode in the second substrate. This three-dimensional stacking arrangement increases the effective capacitance area without expanding the planar footprint, thereby maintaining aperture ratio while achieving sufficient storage capacitance.
Solution Approach 2:
The patent implements a nested capacitor configuration where the common voltage line serves as a shared electrode for both the first and second capacitors. The first capacitor and second capacitor are nested around the common voltage line, with the first pixel electrode and second pixel electrode respectively forming the other electrodes. This nested arrangement maximizes the use of available space and increases storage capacitance without requiring additional lateral space that would reduce aperture ratio.
2Measurement precision
If the pixel pitch is reduced to increase resolution, then the resolution is improved, but the aperture ratio becomes a bottleneck
Solution Approach 1:
The stacked capacitor structure utilizing multiple substrates and vertical stacking enables increased storage capacitance within a reduced planar area. This three-dimensional configuration allows the pixel structure to maintain sufficient capacitance even when the pixel pitch is reduced for higher resolution displays, thereby removing the aperture ratio bottleneck that typically limits resolution improvement.
3Reliability
If the facing area is increased to ensure storage capacitance, then the storage capacitance is improved, but the aperture ratio is restricted
Solution Approach 1:
The patent employs a multi-layer stacked capacitor architecture that extends the capacitance-forming structure in the vertical dimension rather than expanding the horizontal facing area. By stacking capacitors between different substrates and utilizing the common voltage line as a shared electrode, the effective capacitance area is increased three-dimensionally while the planar aperture ratio is preserved.
Solution Approach 2:
The nested capacitor design allows multiple capacitance elements to be arranged around the common voltage line in a compact configuration. The first and second capacitors are nested in space, sharing the common voltage line electrode, which increases the total storage capacitance without requiring a proportionally larger facing area, thereby maintaining a high aperture ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances storage capacitance while decreasing the common voltage line width, effectively increasing the aperture ratio and maintaining desired luminance levels.
Implementation Method 1
the gate insulating layer and the passivation layer interposed therebetween, respectively, so as to form a storage capacitance
Data Source
AI summary
According to the present disclosure, there are disclosed a pixel structure, a dual-gate pixel structure and a display device. The pixel structure comprises: a thin film transistor, a passivation layer that is located over the thin film transistor, an upper pixel electrode that is located over the passivation layer, a lower pixel electrode that is located under a gate insulating layer of the thin film transistor; and a common voltage line that is located between the passivation layer and the gate insulating layer. The common voltage line overlaps with the lower pixel electrode and the upper pixel electrode at least in part with the gate insulating layer and the passivation layer interposed therebetween, respectively, so as to form a storage capacitance.