Dual-Gate Planar Transistor with Self-Aligned Dielectric
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Solution Overview
Problem
Current transistor manufacturing technologies face challenges in cost efficiency and parasitic capacitance issues, particularly in producing transistors with two independent planar gates, which require improved decoupling and reliable fabrication at competitive costs.
Innovation Solution
A planar transistor device with two independent gates is developed, featuring a semiconductor channel and a dielectric zone made of silicon oxide between the gates, which is self-aligned and formed through selective oxidation, reducing parasitic capacitance and achieved using a single lithography operation for excellent geometry and gate alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a process for manufacturing transistors with two independent gates of the planar type is used, then the transistor structure is achieved, but the manufacturing cost increases
Solution Approach 1:
The patent merges the formation of the dielectric zone and channel definition into a single selective oxidation step that occurs during gate formation. This integration eliminates separate processing steps for creating the dielectric zone and defining the channel, thereby reducing manufacturing complexity and cost while achieving the dual-gate transistor structure.
Solution Approach 2:
The selective oxidation process automatically defines both the dielectric zone and the channel region simultaneously through the same processing step. The oxidation self-aligns to create the proper spatial relationship between the gates and the channel, eliminating the need for additional alignment steps and reducing manufacturing cost.
2Device complexity
If conventional transistor manufacturing is used, then production is simpler, but parasitic capacitance between gates increases
Solution Approach 1:
The patent extracts the harmful parasitic capacitance by introducing a dielectric zone between the two gates. This dielectric zone is created through selective oxidation of the semiconductor material in the region between the gates, effectively removing the capacitive coupling that would otherwise exist between the gates.
Solution Approach 2:
The dielectric zone acts as an intermediary element between the two gates, preventing direct capacitive coupling. This intermediate dielectric layer is formed by selective oxidation and serves to electrically isolate the gates while maintaining the structural integrity of the transistor.
3Manufacturing precision
If multiple lithography operations are used to define gates and channel, then alignment precision improves, but manufacturing complexity increases
Solution Approach 1:
The patent combines the definition of the gate structure and the channel/dielectric zone into a single lithography operation. The lithography pattern defines both the gate electrodes and the regions that will undergo selective oxidation to form the dielectric zone and channel, eliminating the need for separate alignment steps.
Solution Approach 2:
The lithography step performs preliminary definition of both the gate locations and the oxidation zones simultaneously. By pre-defining the pattern that will guide both gate formation and selective oxidation in one step, the process achieves precise alignment without requiring subsequent alignment operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and achieves excellent isolation between gates, resulting in a high-quality transistor with improved decoupling and cost-effective fabrication.
Implementation Method 1
The dielectric zone may be obtained by oxidation of part of the material constituting the semiconductor channel
Implementation Method 2
The selective oxidation may comprise an implantation of oxygen ions
Implementation Method 3
the dielectric zone is formed by transformation annealing of the oxidized material. This promotes suitable diffusion of oxygen into the material that has to be oxidized
Implementation Method 4
the dielectric zone is formed by transformation annealing of the oxidized material
Data Source
AI summary
A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.