Dual-Gate Vertical Transistors for Better Gate Overlap
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Solution Overview
Problem
Planar thin film transistors face challenges in scaling due to material property limitations and process control issues, while vertical devices suffer from insufficient source/drain-to-gate overlap, impacting device performance.
Innovation Solution
The formation of vertical field effect transistors with a dual gate configuration, including an inner gate electrode embedded in a dielectric pillar between a bottom and top electrode, and an outer gate electrode, providing increased channel width and on-current per device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If planar thin film transistors are used, then low temperature processing is achieved, but device scaling is limited due to material limitations and process control
Solution Approach 1:
The patent transitions from planar (2D) transistor architecture to vertical (3D) architecture, enabling the channel to extend in the vertical dimension rather than only lateral dimensions. This dimensional change allows continued scaling of device density while maintaining compatibility with low-temperature oxide semiconductor materials, as the vertical channel provides better control over the conductive path without requiring further lateral miniaturization that would exacerbate material and process limitations.
2Productivity
If vertical transistors are used, then device density is increased, but source/drain-to-gate overlap is insufficient, impacting device performance
Solution Approach 1:
The patent implements a dual-gate vertical transistor structure where an inner gate electrode is nested within a dielectric pillar that is surrounded by an outer gate electrode. This nested configuration allows both gates to independently control the vertical channel, providing enhanced electrostatic control and improved source/drain-to-gate overlap without compromising device density. The inner gate can be positioned closer to the channel region, increasing the effective overlap area while maintaining the vertical architecture's high density advantage.
Data Source
AI summary
A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.