Dual-Integrator Oscillator Circuit for Comparator Delay Cancellation
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Solution Overview
Problem
The existing oscillator circuit is sensitive to comparator mismatch and process variations, leading to power consumption issues and frequency instability, with parasitic capacitances affecting the output frequency.
Innovation Solution
The oscillator circuit incorporates integrators with switchable current sources and a comparator unit that alternates between two integrators, using a flip-flop to control the switching, reducing power consumption and sensitivity to comparator mismatch and parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional oscillator circuit with single integrator and comparator is used, then circuit structure is simple, but output frequency is sensitive to comparator mismatch and process variations
Solution Approach 1:
The oscillator circuit is segmented into two symmetric integrator units (first integrator unit 100 and second integrator unit 200) that alternate operation. Each integrator has identical structure with current sources, switches, and capacitors. This segmentation creates redundancy that compensates for comparator mismatch and process variations, improving frequency stability while maintaining reasonable circuit complexity through systematic duplication.
Solution Approach 2:
The circuit dynamically changes operating parameters by alternating between two integrators. During each half-cycle, one integrator is active while the other is inactive, and their roles swap periodically. This parameter switching approach allows the system to average out process variations and comparator mismatches over time, achieving better frequency stability without significantly increasing complexity.
2Reliability
If continuous operation of integrator is maintained, then output frequency is stable, but power consumption increases
Solution Approach 1:
The oscillator employs periodic action by alternating between two integrator units in half-cycle intervals. The first integrator operates during one half-cycle while the second is inactive, then they switch roles in the next half-cycle. This periodic switching maintains continuous oscillation output (ensuring frequency stability) while allowing each integrator to rest periodically, thereby reducing overall power consumption compared to continuous operation of a single integrator.
Solution Approach 2:
While individual integrators are switched on and off periodically, the oscillation function continues without interruption through the alternating operation of the two integrators. The output waveform maintains continuity and stability because one integrator is always active when the other is inactive. This achieves both frequency stability and reduced power consumption by distributing the continuous operation load across multiple components.
3Reliability
If comparator size is increased to reduce mismatch, then frequency stability improves, but parasitic capacitances increase affecting output frequency
Solution Approach 1:
The comparator function is segmented across two comparators (first comparator 151/second comparator 152 in first integrator unit, third comparator 251/fourth comparator 252 in second integrator unit) that operate alternately. This segmentation allows each comparator to be smaller in size, reducing individual parasitic capacitances. The alternating operation and symmetric structure compensate for individual comparator variations, maintaining frequency stability without requiring large comparators with high parasitic capacitances.
Data Source
AI summary
The oscillator circuit comprises first and second integrator units with a first capacitor charged at a first integration node and a second capacitor charged at a second integration node. A comparator unit is arranged between a first switching unit, which is connected to the integration nodes and to a reference signal (VREF), and a second switching unit. The comparator unit compares a signal from the first or second integration node with the reference signal. The second switching unit is connected to a logic unit configured to provide signals controlling the first integrator unit, the second integrator unit, the first switching unit and the second switching unit, so that a periodic operation is generated by alternatingly activating the first integrator unit and the second integrator unit.