Dual-Layer Data Line Architecture for Memory Throughput

The patent introduces a third dimension by stacking data lines vertically across multiple conductive layers. Specifically, first data lines are formed in a first conductive layer while second data lines are formed in a second conductive layer above it, enabling three-dimensional integration. This dimensional transition allows concurrent access to multiple memory cells through different layers, thereby increasing data throughput without proportionally increasing planar area or device complexity.

The patent segments the data line function across multiple conductive layers, with each layer containing specific data lines that access different memory cell regions. The first data lines in the first conductive layer and second data lines in the second conductive layer operate semi-independently, allowing parallel data transmission channels. This segmentation enables higher throughput by dividing the data access function across multiple spatial segments.

The patent merges multiple data line functions into a stacked architecture where first and second data lines occupy different vertical layers but serve complementary access functions. By combining these layers into a single integrated memory structure, the patent achieves higher throughput without linearly increasing power consumption, as shared control circuitry and overlapping signal paths reduce redundant energy expenditure.

The patent employs periodic switching between different data line sets in the stacked architecture. During read operations, alternating between first data lines and second data lines allows time-multiplexed access patterns that reduce simultaneous switching activity. This periodic activation reduces peak power consumption while maintaining high average throughput through efficient operation scheduling.