Dual-Layer Eutectic Electrode for Flip-Chip LED Void Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The eutectic bonding process for flip-chip LED chips results in low package yield due to high eutectic void ratios, which are caused by the non-flatness of the eutectic metal layer surface, leading to poor eutectic quality and increased production costs.
Innovation Solution
A dual-layer eutectic electrode structure is introduced, comprising a first eutectic layer with a concave-convex shape and a second eutectic layer with a flat surface, ensuring that the second eutectic layer does not overlap with the metal layers, thereby forming a flat eutectic plane and reducing void ratios during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer eutectic metal structure is used, then the process is simple, but the surface flatness is poor leading to high void ratios
Solution Approach 1:
The electrode structure is divided into two distinct layers: a first eutectic metal layer providing electrical connection, and a second eutectic metal layer providing a flat bonding surface. This segmentation resolves the contradiction by assigning different functional requirements to different layers, achieving both process simplicity and surface flatness.
Solution Approach 2:
The solution transitions from a single-layer structure to a two-layer structure, adding a vertical dimension to the design. The first layer handles electrical connectivity while the second layer addresses surface flatness, effectively using dimensional expansion to resolve the functional conflict.
2Adaptability or versatility
If Au-stub bumping process is used, then flexibility is high, but equipment cost and production cost are high
Solution Approach 1:
The patent replaces expensive Au-stub bumping with a more economical eutectic bonding approach using low-cost eutectic metals. The process uses standard reflow soldering equipment rather than specialized ultrasound pressing equipment, significantly reducing both equipment investment and material costs while maintaining process flexibility.
3Productivity
If eutectic bonding is used, then production efficiency is high, but surface flatness requirement is high leading to low yield
Solution Approach 1:
By segmenting the electrode into two layers with distinct functions, the patent eliminates the need for high surface flatness requirements. The first layer maintains electrical connectivity while the second layer provides the flat bonding surface, allowing eutectic bonding to proceed efficiently without stringent flatness controls.
Solution Approach 2:
Different regions of the electrode structure are assigned different qualities: the first eutectic metal layer is optimized for electrical conductivity and connection strength, while the second eutectic metal layer is optimized for surface flatness and bonding quality. This local differentiation resolves the contradiction between production efficiency and surface flatness requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the package yield and current stability of flip-chip LED chips by ensuring strong eutectic bonding and uniform current spreading without altering the package substrate, thus improving production efficiency and reducing costs.
Implementation Method 1
the selected eutectic metal is fabricated over the chip through evaporating or sputtering; the chip is pre-fit over the package substrate through low-temperature scaling powder, and reflowed at melting point higher than that of the eutectic metal layer so that the chip is connected to the package substrate
Data Source
AI summary
A light emitting diode includes: a light emitting layer arranged on at least part of a first semiconductor layer, and a second semiconductor layer; a local defect region over a portion of the second semiconductor layer and extending downward to the first semiconductor layer; a metal layer over a portion of the second semiconductor layer; an insulating layer covering the metal layer, the second and first semiconductor layers in the local defect region, with opening structures over the local defect region and the metal layer, respectively; and an electrode structure over the insulating layer and having a first layer and a second layer, and including a first-type electrode region and a second-type electrode region; wherein an upper surface and a lower surface of the first layer are not flat, and a lower surface of the second layer are both flat.