Dual-Level Pixel Circuit Layout for Low-Noise Image Sensors
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Solution Overview
Problem
Modern image sensors face challenges with low conversion gain and high read noise due to complicated metal routing and large parasitic capacitance in shared pixel circuit designs, particularly as pixel size shrinks below 2 μm.
Innovation Solution
The implementation of a dual pixel circuit design with transistors disposed on different levels, separated by conductors on wafers, reduces floating node routing and parasitic capacitance, improving conversion gain and lowering read noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared pixel circuit design is used to reduce device complexity, then the number of transistors per pixel is reduced, but parasitic capacitance increases and conversion gain decreases
Solution Approach 1:
The pixel array is divided into multiple independent pixel circuits, each with its own transistors and signal processing path. This segmentation allows each pixel circuit to be optimized independently, reducing parasitic capacitance while maintaining low device complexity through the shared readout architecture.
Solution Approach 2:
Transistors are disposed on different levels (vertical stacking) rather than all on the same plane. This three-dimensional arrangement reduces the horizontal routing distance and parasitic capacitance between components while maintaining compact pixel area, thereby improving conversion gain without increasing device complexity.
2Area of moving object
If pixel size is reduced to increase pixel density, then more pixels fit in the sensor area, but metal routing becomes complicated and parasitic capacitance increases
Solution Approach 1:
By stacking transistors on different levels vertically, the patent reduces the horizontal space required for routing metals between components. This vertical integration simplifies metal routing complexity while enabling smaller pixel areas and higher pixel density.
Solution Approach 2:
The dual pixel circuit design uses shared readout paths and common signal processing components for multiple pixels. This multi-functional approach reduces the amount of metal routing required per pixel, simplifying the overall routing complexity while maintaining small pixel dimensions.
3Ease of manufacture
If transistors are disposed on the same level to simplify manufacturing, then fabrication is easier, but floating node routing increases and read noise increases
Solution Approach 1:
Transistors are arranged on different vertical levels rather than all on the same horizontal plane. This vertical stacking reduces the horizontal distance for floating node routing, minimizing parasitic capacitance and associated read noise while maintaining manufacturability through standard multi-layer semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances image quality by reducing metal routings and parasitic capacitance, leading to improved conversion gain and lower read noise.
Implementation Method 1
Each of the plurality of pixels includes at least one photodiode
Data Source
AI summary
An image sensor includes a sensing unit. The sensing unit includes a plurality of pixels. Each of the plurality of pixels includes at least one photodiode, at least one first transistor and a first source follower transistor. The sensing unit further includes a plurality of second transistors and a second source follower transistor. In each of the plurality of pixels, the at least one photodiode is electrically connected to the first source follower transistor at least through the at least one first transistor, and electrically connected to the second source follower transistor at least through at least one corresponding second transistor among the plurality of second transistors.