Dual-Loop Referenceless CDR for Jitter-Tolerant Clock Recovery
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Solution Overview
Problem
Conventional referenceless clock and data recovery (CDR) schemes in optical communication systems face challenges in achieving high jitter tolerance and efficiency, particularly at high bit rates like 9 GBPS, due to limited capture range and component complexity, which affects the reliability and power consumption of the receiver.
Innovation Solution
A dual-loop CDR circuit with a phase-locked loop (PLL) and a frequency-locked loop (FLL) is implemented, utilizing a frequency detector (FD) with fewer components, including four flip-flops and two AND gates, to enhance jitter tolerance and reduce power consumption, allowing for accurate clock recovery without a separate clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional referenceless CDR schemes use traditional frequency detectors, then clock recovery can be achieved, but component complexity and power consumption increase
Solution Approach 1:
The CDR circuit is divided into two independent loops: a frequency-locked loop (FLL) for initial frequency acquisition and a phase-locked loop (PLL) for fine phase tracking. This segmentation allows each loop to be optimized independently, with the FLL using a simplified frequency detector that requires fewer components while the PLL handles the precision requirements.
Solution Approach 2:
The FLL acts as an intermediary between the incoming data stream and the PLL. It first acquires the frequency and provides a preliminary clock signal to the PLL, which then refines the phase. This intermediary approach allows the use of a simpler frequency detector in the FLL stage without compromising overall system reliability.
2Use of energy by stationary object
If conventional referenceless CDR schemes use traditional frequency detectors, then clock recovery can be achieved, but power consumption increases
Solution Approach 1:
By segmenting the CDR function into FLL and PLL stages, the power-intensive operations are concentrated in the PLL stage which handles fine phase tracking. The FLL stage uses a simplified frequency detector with fewer components (four flip-flops and two AND gates) that consumes less power while providing sufficient frequency acquisition capability.
Solution Approach 2:
The FLL performs partial frequency detection and correction, handling the coarse frequency acquisition task. This allows the system to achieve acceptable jitter tolerance through the combined action of FLL and PLL, rather than requiring the frequency detector to perform all functions, thereby reducing its complexity and power consumption.
3Device complexity
If the CDR circuit uses fewer components, then power consumption and complexity reduce, but capture range may be limited
Solution Approach 1:
The capture range requirement is segmented between two loops: the FLL provides a wide capture range for initial frequency acquisition using a simplified frequency detector, while the PLL provides fine-tuning capability for precise phase locking. This segmentation allows each loop to be optimized for its specific function, with the FLL handling large frequency offsets and the PLL handling small adjustments.
Solution Approach 2:
The FLL performs preliminary frequency acquisition and correction before the PLL begins operation. This preliminary action brings the clock signal within the capture range of the PLL, enabling the simplified frequency detector in the FLL to handle the initial wide-range frequency search without requiring the full complexity needed for fine phase tracking.
Data Source
AI summary
A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/â0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits.