Dual-Loop Clock Recovery for Repeating Pattern Frequency Lock

The patent divides the timing recovery function into two separate loops: a frequency acquisition loop that operates at full speed to capture frequency offsets, and a phase adjustment loop that operates at one-fourth the symbol rate to refine phase alignment. This segmentation allows each loop to be optimized independently, achieving high precision without requiring all components to operate at full speed, thus reducing overall power consumption and complexity.

The patent implements dynamic switching between different operating modes. The frequency acquisition loop is active during initial acquisition and can be disabled once locked, while the phase adjustment loop operates continuously at a reduced rate. This dynamic operation allows the system to adapt its complexity and power consumption based on the current operational state, maintaining precision when needed while reducing overhead during steady-state operation.

The patent employs dynamic operation where the frequency acquisition loop runs at full symbol rate during initial acquisition to quickly establish frequency lock, then transitions to a phase adjustment loop that operates at one-fourth the symbol rate for ongoing phase refinement. This dynamic scaling of operational complexity based on acquisition state enables high-speed operation when needed while significantly reducing power consumption during steady-state transmission.

The phase adjustment loop operates periodically at one-fourth the symbol rate rather than continuously at full rate. This periodic operation maintains adequate phase alignment while reducing the computational burden and power consumption by a factor of four in the phase adjustment path, enabling high-speed operation with reduced energy requirements.

The patent segments the error detection and correction functions into two specialized loops. The frequency acquisition loop uses a simplified error detector that works reliably with repeating patterns like 1010, while the phase adjustment loop uses a different error detection approach optimized for phase refinement. This segmentation allows each loop to be tailored for its specific function, maintaining reliability across all data patterns without requiring complex universal logic.

The patent introduces an intermediary mechanism where the frequency acquisition loop first establishes reliable frequency lock using pattern-independent detection, then transfers control to the phase adjustment loop for fine-tuning. This intermediary frequency acquisition stage acts as a bridge that ensures reliable operation during repeating patterns before transitioning to the more sophisticated phase adjustment phase, thereby maintaining both simplicity and reliability.