Dual-Loop LDO Regulator for PSRR and Quiescent Current Tradeoffs
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Solution Overview
Problem
Existing low-dropout (LDO) regulators face challenges in maintaining power supply rejection ratio (PSRR), quiescent current, and loop bandwidth tradeoffs, especially when the voltage source is close to the output voltage.
Innovation Solution
A low-dropout regulator incorporating an analog low-dropout (ALDO) circuit assisted by a digital low-dropout (DLDO) circuit that senses operating information of the ALDO circuit, such as current and gate voltage, to adjust output current and capacitance, thereby maintaining the ALDO circuit at its desired operation point without directly referencing the output voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage source drops lower and lower to achieve low-dropout operation, then the voltage difference between input and output is reduced, but the power supply rejection ratio deteriorates
Solution Approach 1:
The patent divides the LDO regulator into two independent control loops: an analog control loop that directly regulates the output voltage, and a digital control loop that separately regulates the power MOS current based on sensed operating information. This segmentation allows each loop to optimize for its specific function without interfering with the other, enabling the digital loop to maintain PSRR by controlling input current independently of the analog voltage regulation.
Solution Approach 2:
The patent introduces a current-sensing resistor and sensing circuit as intermediaries between the power MOS and the digital controller. These intermediaries convert the power MOS current into a measurable voltage signal that the digital controller can use to indirectly sense the operating state of the analog loop and adjust the input current accordingly, thereby maintaining PSRR without directly measuring the output voltage.
2Use of energy by moving object
If the quiescent current is reduced to improve power efficiency, then power consumption decreases, but the ability to maintain regulation under varying loads is compromised
Solution Approach 1:
The patent implements dynamic quiescent current management where the digital controller continuously monitors the operating information of the analog loop and dynamically adjusts the quiescent current of the power MOS based on actual load conditions. When the load is light, the digital controller reduces the quiescent current to minimize power consumption; when the load increases, it increases the quiescent current to maintain proper regulation, thus resolving the contradiction between low quiescent current and regulation capability.
3Speed
If the loop bandwidth is increased to improve response speed, then the regulation response improves, but the power supply rejection ratio deteriorates
Solution Approach 1:
The patent segments the control function into two independent loops with different bandwidth characteristics: the analog loop provides fast voltage regulation response, while the digital loop provides slower but more selective current control with better PSRR. This segmentation allows the system to achieve fast response through the analog loop while maintaining good PSRR through the digital loop's selective filtering of power supply noise.
Solution Approach 2:
The patent changes the control parameter from direct output voltage feedback to indirect power MOS current sensing. By sensing the current of the power MOS and using it as the control parameter for the digital loop, the system can adjust the input current to compensate for power supply variations without introducing high-frequency noise that would degrade PSRR, thus achieving both fast response and good rejection ratio.
Data Source
AI summary
A low-dropout (LDO) regulator having an analog low-dropout (ALDO) regulating circuit assisted by a digital low-dropout (DLDO) regulating circuit is shown. The DLDO regulating circuit is coupled to the ALDO regulating circuit, and senses operating information that shows if the ALDO regulating circuit is within its operating region. The DLDO regulating circuit assists the ALDO regulating circuit based on the operating information of the ALDO regulating circuit instead of an output voltage at the output terminal of the LDO regulator.