Dual Mask Lithography for Random Logic Design Density
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the design area of random logic circuits due to limitations in feature size scaling, particularly as feature sizes approach or exceed the wavelength of illumination sources, and traditional methods for SRAM cells are not applicable to random logic fabrication due to data partitioning complexities.
Innovation Solution
A method involving a dual mask lithography process is used, where a hard mask is deposited above a gate electrode layer, and two photoresist layers are exposed using different masks to form lines and spaces along cell boundaries, allowing for the reduction of design area without the restrictive data partitioning required in traditional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional single mask lithography is used, then the fabrication process is simple, but the design density cannot be increased beyond minimum feature size limits
Solution Approach 1:
The patent divides the patterning process into two separate mask steps. The first mask defines initial gate patterns, and the second mask creates additional spaces along cell boundaries. This segmentation allows achieving higher design density by exploiting cell edges that would be inaccessible in a single mask process, directly resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent transitions from single-layer patterning to multi-layer patterning by introducing a second mask step that operates on the same layer. This dimensional change in the process space (adding a second patterning dimension) enables the formation of additional features along cell boundaries, increasing design density without violating minimum feature size constraints.
2Manufacturing precision
If dual mask lithography is used to increase design density, then space along cell boundaries is reduced, but data partitioning becomes restrictive and difficult
Solution Approach 1:
The patent applies local quality by making the second mask's effect localized to cell boundary regions only. The second mask specifically targets and creates spaces along cell boundaries without affecting internal cell patterns. This localized approach increases design density in border regions while minimizing the impact on overall data partitioning complexity, as the majority of the design space remains unchanged.
3Area of moving object
If feature size is scaled down to increase density, then more components fit on chip, but illumination wavelength limitations prevent further scaling
Solution Approach 1:
The patent applies preliminary action by pre-defining pattern regions with the first mask before applying the second mask. The first mask establishes the primary gate patterns at the minimum feature size, and then the second mask adds additional spacing features. This sequential approach allows the system to work within illumination wavelength limitations while still achieving higher effective density through clever pattern arrangement rather than further feature size reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases design density by reducing the space required along border regions, addressing issues of line end shortening and CD tolerance, thereby improving the feasibility and performance of random logic fabrication.
Implementation Method 1
A first photoresist is formed on the hard mask. A first mask is used to expose the first photoresist layer... A second photoresist layer is formed on the hard mask. A second mask is used to expose the second photoresist layer
Implementation Method 2
a hard mask is deposited above a gate electrode layer
Implementation Method 3
The hard mask is then etched... The hard mask is etched again
Data Source
AI summary
One embodiment of the present invention relates to a method for which a two mask lithography process can be used to reduce design density. The two mask process uses a first mask to expose a first photoresist layer located above a hard mask layer. The first photoresist is exposed in such a way that the level forms one or more lines, on opposite sides of a cell boundary. The hard mask is then etched. A second photoresist layer is deposited above the hard mask. The second mask is used to expose the second photoresist layer in such a way that a space is formed along the cell boundary equal to the minimum space of the level as required by the design rules. The hard mask is then etched again. The hard mask is subsequently used to pattern the layer below it. Other methods and structures are also disclosed.