Dual Mask Strategy for Semiconductor Gate Structure Protection
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Solution Overview
Problem
Conventional methods for forming non-volatile memory devices often damage gate structures during the source line defining process, leading to deteriorated profiles and reliability issues due to dry etching and ion implantation.
Innovation Solution
A method involving the use of a dual mask comprising a patterned photoresist layer and hard mask patterns to protect the stacked structures during etching and ion implantation, reducing damage and transforming polycrystalline silicon to amorphous silicon, thereby improving charge storage reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single patterned photoresist layer is used as a mask for defining a source line, then the source line can be formed, but the gate structures are easily damaged during dry etching and ion implantation, deteriorating the profile and reliability
Solution Approach 1:
The single photoresist mask is segmented into a dual-mask system: a first photoresist layer for initial patterning and a second photoresist layer for subsequent processing. This segmentation allows the first mask to be removed after defining the source line, while the second mask protects gate structures during ion implantation, resolving the contradiction between ease of manufacture and reliability
Solution Approach 2:
The source line is defined in advance using the first photoresist mask before the gate structures undergo ion implantation. This preliminary action allows the source line to be formed while preserving the gate structures for later protection by the second mask, eliminating the damage that would occur if a single mask were used throughout all processes
2Manufacturing precision
If dry etching is used to define the source line, then the source line pattern can be formed, but the gate structure profile is deteriorated
Solution Approach 1:
The etching process is segmented into two stages: first, the source line is defined by etching through the first photoresist mask; second, the gate structures are protected by the second photoresist mask during subsequent etching. This segmentation allows precise source line definition while preserving gate structure profiles
Solution Approach 2:
The second photoresist mask acts as an intermediary protective layer between the etching process and the gate structures. It allows the etching to proceed for source line definition while mediating protection to the gate structures, preventing profile deterioration
3Ease of manufacture
If ion implantation is performed to form doped regions, then the doped regions can be created, but the gate structures suffer from ion bombardment damage transforming polycrystalline silicon to amorphous silicon
Solution Approach 1:
The masking process is segmented into two distinct photoresist layers: the first mask enables doped region formation through ion implantation, while the second mask is specifically designed to protect gate structures during this process. This segmentation allows doped region formation while preventing ion bombardment damage to gates, thereby maintaining charge storage reliability
Solution Approach 2:
The second photoresist mask serves as an intermediary protective barrier during ion implantation. It allows ions to reach the substrate for doped region formation while blocking ions from damaging the gate structures, thus enabling doped region creation without compromising charge storage reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual mask approach minimizes etching and ion bombardment damage, maintaining vertical sidewalls and reducing the transformation of polycrystalline silicon to amorphous silicon, resulting in enhanced charge storage reliability and device performance.
Implementation Method 1
An ion implantation process is performed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a doped region in the substrate around the trench
Implementation Method 2
the step of forming the trench in the substrate includes performing an anisotropic etching process
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. At least two separated stacked structures and at least two hard mask patterns respectively on the stacked structures are formed on a substrate. A patterned mask layer is formed on the substrate. The patterned mask layer has an opening which exposes a portion of top surfaces of the hard mask patterns and a portion of the substrate between the stacked structures. The exposed portion of the substrate is removed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a trench in the substrate. An ion implantation process is performed by using the patterned mask layer and the hard mask patterns as a mask, so as to form a doped region in the substrate around the trench.