Dual Metal Gate Work Function Control for 3D Transistors
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Solution Overview
Problem
The integration of dual work function metal gate electrodes in semiconductor devices is challenging, particularly in controlling the work function value, especially for three-dimensional transistor devices, which requires a work function value around mid-gap by about 200 mV.
Innovation Solution
A method involving the formation of metal gate electrodes by reacting a first-metal-containing material with a second-metal-containing material on a gate dielectric, using materials like Al2O3 and TaN, TiN, WN, or MoN to achieve a work function value ranging from 4.35 eV to 5.0 eV, applicable to both PMOS and NMOS transistors, including three-dimensional FinFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal gate electrodes are used to reduce gate depletion, then device performance is improved, but control of work function value becomes difficult
Solution Approach 1:
The gate electrode is segmented into multiple layers with different materials (e.g., TiN layer and W layer) to independently control different aspects of gate functionality. This segmentation allows one layer to provide low work function while another provides stability, resolving the contradiction between performance and control precision
Solution Approach 2:
The invention uses composite metal gate structures combining different materials (such as TiN-W composite) to achieve properties that neither material alone can provide. The composite structure enables precise work function control while maintaining high device performance, directly addressing the technical contradiction
2Reliability
If dual work function metal gate electrodes are integrated, then low threshold voltages are achieved, but integration difficulty increases
Solution Approach 1:
The gate electrode structure is prepared in advance with specific material layers deposited and patterned before final device assembly. This preliminary preparation of dual-work-function gates simplifies the integration process by pre-configuring the complex multi-layer structure, reducing manufacturing difficulty while achieving low threshold voltages
Solution Approach 2:
The invention controls work function values by adjusting material composition ratios and layer thicknesses during deposition. By changing these parameters systematically, the patent achieves precise control over threshold voltages for both PMOS and NMOS devices, making dual work function integration more manageable
3Reliability
If work function value is controlled for three dimensional transistor devices, then device performance is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode structure is optimized with different material properties at different locations and depths. The multi-layer composition provides locally tailored electrical characteristics that enhance three-dimensional device performance while the systematic deposition process maintains manufacturing precision through controlled material placement
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows precise control of work function values for dual metal gate electrodes, enhancing the performance of CMOS transistors and three-dimensional devices by achieving the desired threshold voltages, thereby improving device performance.
Implementation Method 1
By reacting the first-metal-containing material with an overlaid portion of the second-metal-containing layer, a first gate material can be formed
Data Source
AI summary
Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The stacked layers can include a first-metal-containing material such as Al2O3, and/or AlN overlaid by a second-metal-containing material such as TaN, TiN, WN, MoN or their respective metals. The reaction between the stacked layers can create a metal gate material with a desired work function value ranging from about 4.35 eV to about 5.0 eV. The disclosed methods and structures can be used for CMOS transistors including MOSFET devices formed on a bulk substrate, and planar FET devices or 3-D MuGFET devices (e.g., FinFET devices) formed upon the oxide insulator of a SOI.