Dual MIM Capacitor Structure for Higher Capacitance Density
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Solution Overview
Problem
In semiconductor integrated circuits, the decreasing dimensions of capacitors lead to reduced capacitance, making it challenging to maintain or improve device electrical performance, as increasing capacitance per unit area requires more device space and often involves expensive, environmentally harmful high-k dielectric materials, and insufficient plate separation can result in lower breakdown voltage.
Innovation Solution
A dual MIM capacitor structure is formed by creating a second parallel plate capacitor over a first one, sharing a common capacitor plate, connected in parallel to increase capacitance per unit area without additional mask layers, allowing for adjustment of capacitance by varying overlap surface areas, thus enhancing capacitance range in chip designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitor dimensions are decreased to increase functional density, then device integration is improved, but capacitance per unit area is reduced
Solution Approach 1:
The patent implements a nested capacitor structure where a second capacitor is formed within the same footprint as the first capacitor by sharing a common plate. The second capacitor's first plate is the first capacitor's second plate, allowing both capacitors to occupy overlapping horizontal areas. This nesting approach enables increased total capacitance per unit area without requiring additional lateral space, thereby resolving the contradiction between maintaining capacitance and increasing functional density.
Solution Approach 2:
The patent transitions from a single-plane capacitor arrangement to a multi-dimensional stacked configuration. By forming capacitors in vertical layers with overlapping footprints rather than side-by-side lateral arrangement, the design exploits the vertical dimension to increase capacitance density. This dimensional change allows multiple capacitors to coexist within the same planar footprint, addressing the contradiction between capacitance maintenance and functional density improvement.
2Quantity of substance
If high-k dielectric materials are used to increase capacitance, then capacitance per unit area is improved, but manufacturing cost and environmental harm increase
Solution Approach 1:
The patent changes the structural parameter of the capacitor system by implementing a dual-capacitor nested configuration rather than relying on material parameter changes such as switching to high-k dielectrics. By increasing the number of capacitive elements within the same footprint through clever geometric arrangement and plate sharing, the design achieves higher total capacitance using conventional, environmentally friendly materials, thereby avoiding the costs and environmental issues associated with high-k dielectric materials.
3Quantity of substance
If plate separation is decreased to increase capacitance, then capacitance per unit area is improved, but breakdown voltage is reduced
Solution Approach 1:
The nested capacitor structure allows each capacitor to maintain its own optimized plate separation distance for reliability while achieving high total capacitance through the combination of multiple capacitors. The first capacitor has plate separation sufficient for its voltage requirements, and the second capacitor independently has appropriate separation for its requirements. This modular nested approach enables capacitance scaling without compromising the breakdown voltage characteristics of individual capacitor units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves higher capacitance per unit area while maintaining compatibility with current layout designs and process flows, without the need for additional masks, thereby improving electrical performance and reducing environmental impact.
Implementation Method 1
Metal insulator metal capacitor structure having high capacitance
Implementation Method 2
A first dielectric layer is formed over the first metal layer and a second metal layer is formed over the first dielectric layer. A second dielectric layer is formed over the second metal layer
Data Source
AI summary
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a MIM dual capacitor structure with an increased capacitance per unit area in a semiconductor structure. Without using additional mask layers, a second parallel plate capacitor can be formed over a first parallel plate capacitor, and both capacitors share a common capacitor plate. The two parallel plate capacitors can be connected in parallel to increase the capacitance per unit area.