Dual-Mode PCB Routing for D-PHY and C-PHY Signal Integrity
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Solution Overview
Problem
Existing dual-mode IC chips requiring separate PCBs for D-PHY and C-PHY modes incur double spending in design and manufacturing costs due to the need for distinct layouts.
Innovation Solution
A universal PCB design with assembly option techniques that supports both C-PHY and D-PHY interfaces by configuring connections for D-PHY or C-PHY functions using a single layout, utilizing assembly option modules to route pins to appropriate wires based on the required interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate PCBs are used for D-PHY and C-PHY modes, then signal integrity and impedance matching for each mode are maintained, but design and manufacturing costs double
Solution Approach 1:
The patent implements a universal PCB design where the same physical board can be configured to support both D-PHY and C-PHY interface modes through assembly option modules. The PCB layout includes trace routes and connection points that can be selectively activated depending on the required interface mode, eliminating the need for separate dedicated PCB designs for each mode while maintaining proper signal integrity and impedance matching characteristics for both interfaces
Solution Approach 2:
The patent employs assembly option modules that allow the PCB configuration to be dynamically changed based on the required interface mode. By selecting different assembly configurations (such as different connector placements, trace terminations, or component orientations), the same PCB can be adapted to support either D-PHY or C-PHY modes, providing flexibility without requiring multiple fixed designs
2Ease of manufacture
If a single PCB supports both D-PHY and C-PHY modes, then design and manufacturing costs are reduced, but maintaining signal integrity and impedance matching for both modes becomes more difficult
Solution Approach 1:
The patent divides the PCB into distinct functional zones and trace route segments that can be independently configured for D-PHY or C-PHY modes. The layout separates high-speed signal paths from other circuits and provides dedicated impedance-controlled trace routes for each interface type, ensuring that when a particular mode is selected, its signal integrity requirements are met through properly designed segmented pathways
Solution Approach 2:
The patent applies different local characteristics to different regions of the PCB to accommodate the specific requirements of D-PHY and C-PHY interfaces. This includes varying trace widths, spacing, and impedance values in different areas of the board, and using mode-specific assembly option modules that provide locally optimized signal paths for whichever interface mode is currently activated
Data Source
AI summary
A printed circuit board, PCB, comprising: a first pin pad (PP1), adapted to be connected to a first pin of an integrated circuit, IC, chip, wherein the first pin of the IC chip is a pin for a D-PHY function and a C-PHY function provided by the IC chip; a first wire (W1), adapted as a line for the D-PHY function; a second wire (W2), adapted as a line for the C-PHY function; and a first assembly option module (A1), adapted to provide a first option of connecting the first pin pad (PP1) to the first wire (W1) if the IC chip to be assembled onto the PCB is to provide the D-PHY function, or to provide a second option of connecting the first pin pad (PP1) to the second wire (W2) if the IC chip to be assembled onto the PCB is to provide the C-PHY function.