Dual-Mode PFD Circuit for Faster PLL Frequency Locking
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Solution Overview
Problem
Existing phase lock loop (PLL) circuits face challenges in reducing lock time during frequency switching, as current techniques often require additional analog circuitry, increased power consumption, and modified loop filter components, which complicate the design and increase costs.
Innovation Solution
The implementation of a phase frequency detector (PFD) circuit that operates in two modes: in the first mode, it generates a pulse-width signal proportional to the phase difference, and in the second mode, it holds the control input signal constant for a predetermined time to enhance loop filter current during frequency transitions, thereby reducing lock time without auxiliary charge pumps or modified analog circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional PFD circuit operation is used, then the circuit structure remains simple, but the lock time during frequency switching is long
Solution Approach 1:
The PFD circuit dynamically switches between two operating modes (first mode and second mode) based on the detected phase difference magnitude. During frequency switching when phase difference exceeds the threshold, the circuit transitions to the second mode with enhanced charge pump current to accelerate locking. When locked, it operates in the first mode with normal current, thereby reducing lock time without requiring permanently complex circuitry.
Solution Approach 2:
The invention changes the charge pump current parameter dynamically based on operating conditions. In the first mode, the charge pump operates at normal current level. In the second mode, when phase difference exceeds the threshold, the charge pump current is enhanced to a higher level to speed up the locking process. This parameter change allows the system to achieve fast locking during frequency transitions without permanently increasing power consumption or circuit complexity.
2Loss of time
If additional analog circuitry is added to reduce lock time, then the locking performance improves, but the device complexity and manufacturing cost increase
Solution Approach 1:
The enhanced charge pump circuit serves multiple functions: it operates as a normal charge pump during locked conditions and as an enhanced-speed charge pump during frequency switching. This multi-functionality eliminates the need for separate auxiliary charge pump circuits or additional analog circuitry that would be required by other approaches, thereby reducing manufacturing complexity while achieving fast lock time.
Solution Approach 2:
The PFD circuit automatically detects when frequency switching occurs by monitoring the phase difference between reference and feedback signals. When the phase difference exceeds the threshold, the circuit self-activates the enhanced charge pump mode without requiring external control signals or additional detection circuitry. This self-service capability eliminates the need for auxiliary control circuits and simplifies the overall system design.
3Stability of the object's composition
If charge pump current is reduced to maintain stability near locked condition, then the stability improves, but the lock time during frequency switching increases
Solution Approach 1:
The charge pump current is dynamically adjusted based on the phase difference between reference and feedback signals. During frequency switching when phase difference is large, the enhanced current provides fast locking. When the phase difference falls below the threshold and the system approaches locked condition, the circuit automatically transitions to the first mode with normal current, maintaining stability. This dynamic adjustment resolves the contradiction between fast locking and stable locked condition.
Solution Approach 2:
The circuit prepares for potential frequency switching by maintaining the capability to switch to enhanced charge pump mode at any time. The threshold detection mechanism is continuously active, ready to trigger the enhanced current mode immediately when phase difference exceeds the threshold, ensuring fast response to frequency changes without compromising normal operating stability.
Data Source
AI summary
Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector (PFD) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.