Dual-Mode PLL Loop Filter for Fast Coherent Locking
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Solution Overview
Problem
Existing PLLs face challenges in achieving fast settling time in coherent mode while maintaining reduced power consumption in non-coherent mode, with dynamic capacitor switching causing instability and slow recovery to steady state.
Innovation Solution
A dual mode PLL design using dual LPFs, a time-varying proportional gain, and selectable coherent and non-coherent modes, which includes a dedicated LPF for coherent mode to ensure phase coherency and a PIC with adjustable gain for power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the PLL bandwidth and LPF cut off frequency are increased to achieve faster locking time in coherent mode, then the settling time is reduced, but the power consumption increases and the steady-state stability deteriorates
Solution Approach 1:
The patent implements dynamic switching between two LPF configurations: a first LPF with higher cut-off frequency for fast settling in coherent mode, and a second LPF with lower cut-off frequency for low power consumption in non-coherent mode. This dynamic reconfiguration allows the system to adapt its filtering characteristics based on operational requirements, resolving the contradiction between fast settling and power efficiency.
Solution Approach 2:
The patent changes the cut-off frequency parameter of the LPF dynamically by switching between two different LPF designs. The first LPF has a higher cut-off frequency optimized for fast locking, while the second LPF has a lower cut-off frequency optimized for power savings. This parameter change enables the system to achieve fast settling when needed without incurring continuous power penalties.
2Loss of time
If dynamic capacitor switching is used to increase PLL bandwidth for faster locking, then the settling time is reduced, but charge injection disturbs the PLL loop and slows down steady state recovery
Solution Approach 1:
The patent segments the LPF into two distinct designs (first LPF and second LPF) with different cut-off frequencies, eliminating the need for dynamic capacitor switching within a single LPF. Each LPF is optimized for specific operational modes, and switching between them avoids the charge injection problems associated with dynamic capacitor switching, thereby maintaining steady-state stability.
Solution Approach 2:
The patent introduces a mode selection mechanism that acts as an intermediary between the two LPF configurations. This mediator selects the appropriate LPF based on whether coherent or non-coherent mode is active, avoiding direct dynamic capacitor switching and its associated charge injection disturbances to the PLL loop.
3Reliability
If the same LPF characteristics are used in both coherent and non-coherent modes to maintain steady state stability, then the PLL loop bandwidth and phase margin are consistent, but the settling time in coherent mode is slow
Solution Approach 1:
The patent makes the LPF characteristics dynamic by switching between two different LPF configurations based on operational mode. The first LPF with higher cut-off frequency provides fast settling for coherent mode, while the second LPF with lower cut-off frequency ensures stability for non-coherent mode. This dynamic adaptation resolves the contradiction between fast settling and steady-state stability.
Solution Approach 2:
The patent applies different LPF characteristics locally to different operational modes. The first LPF with higher cut-off frequency is specifically optimized for coherent mode where fast settling is critical, while the second LPF with lower cut-off frequency is optimized for non-coherent mode where power consumption and stability are priorities. This local optimization allows each mode to have its own tailored filtering characteristics.
Data Source
AI summary
A method of operation for a dual mode Phase-Locked Loop (PLL) for phase coherent application includes selecting one of a non-coherent mode and a coherent mode. The non-coherent mode includes controlling a Voltage Controlled Oscillator (VCO) with a first error voltage determined by a first Low Pass Filter (LPF), the first LPF configured to filter a first output of a phase detector, the phase detector configured to determine a phase difference between a reference frequency and a feedback signal derived from a VCO frequency generated by the VCO. The coherent mode includes controlling the VCO with the first error voltage and a second error voltage determined by a second LPF of a Proportional and Integral Controller (PIC) configured to filter the first output of the phase detector and by a time variant proportional gain configured to modify a second output of the second LPF.