Dual-Mode Scan Compression Architecture for SoC Test Optimization
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Solution Overview
Problem
Current scan compression architectures for system-on-chip (SoC) integrated circuits face limitations in balancing test parallelism and time, particularly in complex SoC ICs with embedded flash memory, where high parallelism is needed at the wafer level and low time is required at the package level, leading to increased testing costs.
Innovation Solution
A dual-mode scan hardware architecture with two compressor/decompressor configurations, MINCONF and MAXCONF, is introduced, where MINCONF enables high parallelism during wafer level testing by probing a limited subset of pins and MAXCONF reduces test time by probing all pins during package level testing, allowing for flexible test execution based on specific requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single scan compression architecture is used for both wafer level and package level testing, then the device area is reduced, but the test parallelism at wafer level is limited and test time at package level increases
Solution Approach 1:
The patent implements a dynamic scan compression architecture that can reconfigure between two modes: MINCONF mode for wafer level testing with high parallelism, and MAXCONF mode for package level testing with reduced test time. The architecture dynamically adapts its configuration based on the testing phase, allowing the system to optimize for either parallelism or speed as needed without being locked into a single static configuration.
Solution Approach 2:
The scan compression architecture is segmented into two distinct configurations (MINCONF and MAXCONF) that can be selectively activated. Each configuration is optimized for specific testing requirements, allowing the system to divide the testing process into phases that can be handled by different architectural modes, thereby resolving the contradiction between parallelism and test time.
2Loss of time
If all pins are probed for package level testing, then test time is reduced, but the number of pins required increases
Solution Approach 1:
The architecture dynamically switches between using a limited subset of pins in MINCONF mode for wafer level testing and all available pins in MAXCONF mode for package level testing. This dynamic pin allocation allows the system to use minimal pins when high parallelism is needed and maximize pin utilization when test time is the critical constraint.
3Productivity
If a limited subset of pins is used for wafer level testing, then test parallelism is improved, but test time increases
Solution Approach 1:
The testing process is segmented into two phases: wafer level testing using MINCONF configuration with limited pins for high parallelism, and package level testing using MAXCONF configuration with all pins for reduced test time. This segmentation allows each phase to be optimized independently for its specific requirements.
Data Source
AI summary
A scan compression architecture for a design for a testability compiler used in system-on-chip software design tools includes a first scan architecture including a first scan compressor/decompressor configuration connected to a first predetermined set of pins, and a second scan architecture including a second scan compressor/decompressor configuration connected to a subset of the pins. The first scan architecture is selectively enabled for executing a scan test with a low time. The second scan architecture is for executing a scan test with high parallelism.