A loading set plate sends defective chips directly to retesting, reducing transfers and overall semiconductor test time.
A movable height-adjusting mechanism adapts the socket's support surface for BGA and LGA packages without replacement.
Segmented detecting wires form closed loops around the installation area to localize ceramic substrate cracks with greater reliability.
A probe head routes loopback signals through guide-plate traces between probe pins, shortening paths and improving test signal integrity.
A stacked jig, optical assemblies, and interposer enable pre-packaging electrical tests, helping improve yield and avoid defective final assemblies.
This SoC BIST architecture verifies monitoring circuits by testing supply and reference ranges plus comparator offsets.
The inspection circuitry calculates electrical standards from transistor specifications and flags current-voltage data outside them.
A sensor-reference count difference enables clockless, calibration-free aging detection.
Conductive and convective cooling combine with a communicating pipe to keep chip sockets cold and dry without a large testing chamber.
This equivalent circuit mimics a gridded ion thruster, letting engineers test its power supply assembly under ambient conditions.