Semiconductor Chip Testing with Direct Defect Retesting
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Solution Overview
Problem
Existing semiconductor test processes struggle to efficiently classify semiconductor chips into defective and good products, leading to inefficiencies in the testing and retesting of defective chips, which prolongs the overall testing time.
Innovation Solution
A semiconductor test apparatus with a tray housing, loading and unloading stackers, a test device, and processing circuitry that includes a retest controller to directly transfer defective chips to a loading set plate for retesting, bypassing intermediate storage, thereby optimizing the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If defective semiconductor chips are transferred through intermediate storage before retesting, then the classification process is systematic, but the testing time is prolonged
Solution Approach 1:
The patent extracts the retesting function from the conventional classification pathway by providing a dedicated retesting stage that directly receives defective chips from the classification stage and returns them for retesting, bypassing the need for intermediate storage and reloading through normal loading stackers. This extraction creates a parallel retesting loop that eliminates time-consuming intermediate steps.
Solution Approach 2:
The loading set plate serves as an intermediary component that enables direct transfer of defective chips from the classification stage to the retesting stage. This intermediary structure allows chips to be moved directly between stages without passing through intermediate storage, thereby reducing the overall testing time while maintaining systematic classification.
2Reliability
If multiple transfer stages are used for retesting defective chips, then chip classification is thorough, but the number of transfers increases
Solution Approach 1:
The patent merges the retesting function with the existing classification and testing stages by creating an integrated retesting loop. The loading set plate is incorporated into both the classification stage output and the retesting stage input, allowing defective chips to be directly transferred for retesting without requiring separate intermediate storage and loading operations. This merging reduces the number of transfers while maintaining thorough classification.
3Ease of operation
If defective chips are stored in intermediate storage before retesting, then organization is improved, but unnecessary transfers are created
Solution Approach 1:
The loading set plate is prepared in advance as part of the classification stage infrastructure, positioned to directly receive defective chips and transfer them to the retesting stage. This preliminary preparation eliminates the need for intermediate storage operations during the actual testing process, maintaining organization while improving productivity by reducing unnecessary transfers.
Data Source
AI summary
A semiconductor test apparatus includes a tray housing including a loading stacker, a first unloading stacker, and a second unloading stacker, the loading stacker configured to receive a plurality of semiconductor chips for testing, the first unloading stacker configured to receive any defective semiconductor chip among the plurality of semiconductor chips, and the second unloading stacker configured to receive any good semiconductor chip among the plurality of semiconductor chips, a loader configured to place, on a loading set plate, the plurality of semiconductor chips for testing, and load the plurality of semiconductor chips for testing onto a test tray, and a test device configured to test the plurality of semiconductor chips for testing stacked on the test tray.