Dual-Molded Build-Up Interconnect for FO-WLCSP I/O Density
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Solution Overview
Problem
Fan-out wafer level chip scale packages (FO-WLCSP) have limited input/output (I/O) pin count due to the large size of build-up interconnect structures required for mounting semiconductor dies on one side, which increases manufacturing costs and reduces interconnect capability.
Innovation Solution
The method involves mounting semiconductor dies on both sides of the build-up interconnect structure, with dual-molding and conductive pillars for interconnection, allowing for a more efficient use of the interconnect structure and reducing bump pitch to increase I/O pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor dies are mounted on one side of the build-up interconnect structure, then the structure provides sufficient mounting area, but the structure size becomes large, reducing I/O pin count and increasing manufacturing cost
Solution Approach 1:
The patent transitions from single-sided die mounting to dual-sided die mounting on the build-up interconnect structure. By utilizing both the top and bottom surfaces of the interconnect structure for die attachment, the effective mounting area is doubled without increasing the horizontal footprint of the structure, thereby resolving the contradiction between providing sufficient mounting area and minimizing structure size.
2Ease of manufacture
If semiconductor dies are mounted on one side of the build-up interconnect structure, then the mounting process is simple, but the I/O pin count is limited and manufacturing cost increases
Solution Approach 1:
The invention utilizes the vertical dimension by mounting dies on both the top and bottom surfaces of the build-up interconnect structure. This dual-sided approach effectively doubles the number of I/O pins that can be accommodated without complicating the fundamental mounting process, as each side can be processed independently using standard mounting techniques.
3Area of stationary object
If the build-up interconnect structure is made large to accommodate single-sided die mounting, then sufficient mounting area is provided, but manufacturing cost increases
Solution Approach 1:
By mounting dies on both sides of the build-up interconnect structure, the patent maximizes the utilization of the structure's surface area. This approach provides sufficient mounting area for multiple dies without needing to increase the horizontal dimensions of the structure, thereby reducing material usage and manufacturing cost while maintaining adequate mounting capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of the build-up interconnect structure, decreases manufacturing costs, and enhances the I/O pin count, improving the interconnect capability of FO-WLCSPs.
Implementation Method 1
A first molding compound is formed around the first and second semiconductor dies and the first and second interconnect structures
Data Source
AI summary
A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.