Dual MPEG Video Decoding With Arbiter-Controlled Signal Processing
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Solution Overview
Problem
Conventional video decoding systems for high definition (HD) MPEG video signals from different channels require multiple decoder chips, leading to large chip size and inefficient time division processing, with irregular decoding synchronization and display issues.
Innovation Solution
A dual video decoding system comprising a first and second channel video decoder, a video signal processor, and an arbiter, where the video signal processor performs inverse quantization, inverse discrete cosine transformation, and motion compensation on decoded video streams, and the arbiter grants control to the decoders when idle, optimizing processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two discrete MPEG decoder chips are used to decode video streams from different channels, then decoding capability for multiple channels is achieved, but chip size becomes large
Solution Approach 1:
The patent merges the video decoding functions for multiple channels into a single integrated decoder chip. The decoder includes multiple video decode units that can process video streams from different channels simultaneously or sequentially, eliminating the need for multiple separate decoder chips while maintaining multi-channel decoding capability.
Solution Approach 2:
The decoder is designed with universal functionality to handle video streams from multiple channels through a single device. The video decode units can be dynamically allocated to different channels based on demand, allowing one chip to perform the work of multiple dedicated decoder chips.
2Reliability
If signal processing is performed on video streams with respect to pictures, then complete picture decoding is achieved, but time division efficiency is insufficient
Solution Approach 1:
The patent segments the video stream processing into smaller units called slices within pictures. The video decode units can process multiple slices from different channels in an interleaved manner, improving time division efficiency while ensuring complete picture decoding through proper slice assembly and synchronization.
Solution Approach 2:
The decoder employs dynamic resource allocation where video decode units can be dynamically assigned to different channels and processing tasks based on current workload and channel priorities. This dynamic scheduling optimizes time division efficiency while maintaining complete picture decoding integrity.
3Adaptability or versatility
If decoding is performed using mixed mode of frame picture and field picture or 3:2 pull-down decoding, then versatile decoding formats are supported, but decoding synchronization becomes irregular
Solution Approach 1:
The patent implements feedback mechanisms through synchronization control units that monitor the decoding status of frame and field pictures. The system uses timing information and synchronization signals to adjust the decoding process dynamically, ensuring regular output synchronization even when processing mixed decoding formats like 3:2 pull-down.
Solution Approach 2:
The decoder changes processing parameters dynamically based on the input format. When detecting frame or field picture modes or 3:2 pull-down sequences, the system adjusts timing parameters, scan rates, and processing intervals to maintain regular synchronization output while supporting versatile decoding formats.
Data Source
AI summary
A video decoding system capable of decoding compressed high definition (HD) MPEG video signals incoming from different channels includes a first channel video decoder, a second channel video decoder, a video signal processor and an arbiter, where the first and second channel video decoders decode video streams incoming from different channels to generate decoded video streams and request signals, the video signal processor performs signal processing on the decoded video streams, and the arbiter grants control of the video signal processor to the first and second channel video decoders.