Dual-Oscillator Clock Output Circuit for Crosstalk-Free Frequency Selection
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Solution Overview
Problem
Existing clock signal generating circuits with multiple oscillators suffer from crosstalk and glitch signals when generating clock signals of different frequencies, degrading signal quality and requiring complex circuit switching schemes.
Innovation Solution
A clock signal generating apparatus comprising a first frequency generating circuit, a second frequency generating circuit, and an output circuit with multiplexers controlled by an external bonding pad, allowing for independent output of clock signals with different frequencies without switching, thereby reducing crosstalk and glitch signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two independent oscillators are configured in the same clock signal generating circuit, then two clock signals with different frequencies can be generated, but crosstalk is introduced into the clock signals
Solution Approach 1:
The patent divides the clock signal generation system into separate independent oscillator circuits, each generating its own clock signal through dedicated signal paths. This segmentation isolates the oscillators from each other, preventing crosstalk while maintaining the ability to generate multiple frequencies simultaneously
Solution Approach 2:
The patent introduces separate output buffers and signal path isolation mechanisms as intermediaries between the oscillators and the external circuitry. These intermediaries prevent direct interaction between the oscillator signals, eliminating crosstalk while preserving frequency generation versatility
2Ease of operation
If circuit switching scheme is used to select correct clock signal from different clock signals, then appropriate clock signal can be output, but undesired glitch signals are caused
Solution Approach 1:
The patent assigns each oscillator to its own dedicated output buffer and signal path, eliminating the need for switching between shared resources. This segmentation allows simultaneous output of multiple clock signals without glitch generation, while still enabling selective output through independent buffer control
Solution Approach 2:
The patent prepares multiple independently buffered clock signals in advance, each ready for immediate output. This preliminary preparation eliminates the need for real-time switching operations that would cause glitches, as the correct signal is already prepared and can be selected without transition artifacts
3Adaptability or versatility
If two independent oscillators are configured in the same clock signal generating circuit, then two clock signals with different frequencies can be generated, but qualities of the clock signals are degraded
Solution Approach 1:
The patent implements completely separate signal paths for each oscillator, including independent buffers and output stages. This segmentation prevents signal degradation and interference, maintaining high clock signal quality while enabling multi-frequency generation capability
Solution Approach 2:
The patent introduces dedicated output buffers and isolation circuits as intermediaries between each oscillator and the external world. These intermediaries protect the oscillator signals from loading effects and interference, preserving signal integrity and quality while maintaining versatility
Data Source
AI summary
A clock signal generating apparatus includes a first frequency generating circuit, a second frequency generating circuit, and an output circuit. The first frequency generating circuit is arranged to generate a first clock signal having a first oscillation frequency. The second frequency generating circuit is arranged to generate a second clock signal having a second oscillation frequency. The output circuit is arranged to receive the first and second clock signals. The output circuit is able to output one of the first and second clock signals as an output clock signal according to an oscillation frequency control setting provided by an external bounding pad included within the clock signal generating apparatus.