Dual-Path Digital-to-Time Converter for Low-Spur Phase Detection
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) face issues with quantization noise and non-linearity, particularly when operating near-integer channels, leading to spurious tone generation due to the limited resolution and non-linearity of time-to-digital converters (TDCs), which complicates calibration and increases power consumption.
Innovation Solution
A dual-path digital-to-time converter (DTC) with a delay chain circuit and dynamic element matching (DEM) controller, where each delay cell can switch between fast and slow delay states, coupled with a phase detector, accumulator, and calibration circuit to adjust control signals and compensate for supply noise and mismatches, thereby reducing spurious tones and improving phase measurement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional single-path DTC is used to improve phase detection resolution, then measurement precision is improved, but device complexity and power consumption increase due to complex calibration logic
Solution Approach 1:
The delay chain is divided into multiple parallel paths (first path and second path) with different delay characteristics. Each path processes the clock signal independently through its own delay cells, allowing the system to achieve high resolution phase detection without requiring complex calibration logic by distributing the function across segmented parallel paths.
Solution Approach 2:
Instead of using a single path with complex calibration logic to achieve high precision, the invention inverts the approach by using multiple parallel paths with inherently different delay characteristics. The calibration is simplified by monitoring the accumulator output and adjusting control signals to balance the paths, rather than using complex pre-calibration logic.
2Measurement precision
If a conventional single-path DTC is used to improve phase detection resolution, then measurement precision is improved, but power consumption increases due to complex calibration logic
Solution Approach 1:
The delay chain is divided into multiple parallel paths (first path and second path) with different delay characteristics. Each path processes the clock signal independently through its own delay cells, allowing the system to achieve high resolution phase detection without requiring complex calibration logic by distributing the function across segmented parallel paths.
Solution Approach 2:
Instead of using a single path with complex calibration logic to achieve high precision, the invention inverts the approach by using multiple parallel paths with inherently different delay characteristics. The calibration is simplified by monitoring the accumulator output and adjusting control signals to balance the paths, rather than using complex pre-calibration logic.
3Device complexity
If delay cells operate with fixed delay states to simplify control, then device complexity is reduced, but measurement precision deteriorates due to inability to compensate for supply noise and mismatches
Solution Approach 1:
The delay cells are designed with dynamic control capability, allowing each cell to switch between fast and slow delay states based on control signals from the DEM controller. This dynamic operation enables the system to adapt to supply noise and mismatches by adjusting the delay characteristics in real-time, thereby maintaining high measurement precision while keeping control manageable through the calibration circuit.
Solution Approach 2:
A calibration circuit is implemented that monitors the accumulator output and provides feedback to adjust the control signals supplied to the DEM controller. This feedback mechanism automatically compensates for supply noise and mismatches in the delay chain, maintaining high measurement accuracy without requiring overly complex control logic.
4Adaptability or versatility
If fractional operation is implemented to relax system planning, then adaptability is improved, but spurious tone generation increases due to quantization noise and non-linearity
Solution Approach 1:
The delay chain is divided into multiple parallel paths (first path and second path) with different delay characteristics. Each path processes the clock signal independently through its own delay cells, allowing the system to achieve high resolution phase detection without requiring complex calibration logic by distributing the function across segmented parallel paths.
Solution Approach 2:
The system dynamically changes the delay parameters by switching delay cells between fast and slow delay states based on control signals. This parameter variation allows the DTC to achieve fine resolution for fractional operation while the calibration circuit adjusts these parameters to minimize spurious tones generated during fractional-N multiplication.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3
AI summary
An example digital-to-time converter (DTC) (102) includes: a delay chain circuit (301) having a plurality of delay cells (302) coupled in sequence, the delay chain circuit including a first input (Fref) to receive a first clock signal and a second input (FDCO) to receive a second clock signal; and a DEM controller (310) coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.