Dual-Path PLL Linearization for Low Phase Noise Stability
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Solution Overview
Problem
Existing PLL designs face challenges in achieving low phase noise, limited power consumption, and chip area without sacrificing performance, particularly in multi-antenna systems where phase stability is affected by temperature gradients and PVT variations, leading to increased calibrations and throughput limitations.
Innovation Solution
A dual-path PLL architecture is implemented, with a digital integral path for long-term phase tracking and an analog proportional path for short-term phase correction, using feedback signal delay and additional linear phase detection to linearize the phase error transfer and minimize phase drift, without requiring high-resolution TDCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog PLL is used to achieve low phase noise and reduced design complexity, then phase noise performance is improved, but adaptability to digital algorithms and frequency hopping speed is reduced
Solution Approach 1:
The PLL is divided into two separate paths: an analog proportional path for phase correction and a digital integral path for frequency control. This segmentation allows each path to be optimized for its specific function, combining the advantages of both analog and digital implementations.
Solution Approach 2:
The patent merges analog and digital PLL architectures into a hybrid system where the analog proportional path handles phase error correction while the digital integral path manages frequency adjustments, achieving both low phase noise and digital algorithm compatibility.
2Adaptability or versatility
If a digital PLL is used to support digital algorithms and enable high-speed frequency hops, then adaptability is improved, but phase noise performance deteriorates
Solution Approach 1:
The PLL is divided into two separate paths: an analog proportional path for phase correction and a digital integral path for frequency control. This segmentation allows each path to be optimized for its specific function, combining the advantages of both analog and digital implementations.
Solution Approach 2:
The patent merges analog and digital PLL architectures into a hybrid system where the analog proportional path handles phase error correction while the digital integral path manages frequency adjustments, achieving both low phase noise and digital algorithm compatibility.
3Reliability
If feedback signal delay is added to linearize the phase error transfer function, then phase stability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a delay element in the feedback path that changes the timing parameter of the feedback signal. This delay transforms the non-linear phase error transfer function into a linear one, improving phase stability while adding only a single delay element to the circuit.
4Reliability
If multiple calibrations are performed to compensate for PVT variations in multi-antenna systems, then phase stability is improved, but productivity decreases
Solution Approach 1:
The linearized phase error transfer function enables the PLL to automatically compensate for PVT variations without requiring external calibration procedures. The system self-adjusts to maintain phase stability, eliminating the need for multiple calibrations and preserving throughput.
Data Source
AI summary
A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.