Dual-Path PLL Filter Switching for Faster Lock Acquisition
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Solution Overview
Problem
Dual-path phase locked loops (PLLs) experience prolonged lock times due to time constants associated with the slow control path of the dual-path low-pass filter, which slows down the PLL's ability to align with a new frequency, affecting performance and power savings in semiconductor chips and wireless devices.
Innovation Solution
A dual-path PLL circuit with a low-pass filter comprising a passive second-order lead-lag filter and a first-order lag filter, where the impedance in the second stage is bypassed during lock-acquisition to increase loop bandwidth and gain in the first stage, and then returned to normal when locked, allowing for faster frequency alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the slow control path bandwidth is reduced to provide stable frequency control, then the PLL stability is improved, but the lock time increases significantly
Solution Approach 1:
The patent implements dynamic switching between two control paths: a fast control path for rapid frequency acquisition and a slow control path for stable frequency maintenance. The system transitions from fast to slow control path once frequency lock is achieved, allowing the PLL to adapt its response characteristics based on operational state. This resolves the contradiction by providing both fast lock time during acquisition and stable frequency control during normal operation.
Solution Approach 2:
The control system is segmented into two distinct paths: a fast control path with higher bandwidth for rapid frequency adjustment, and a slow control path with lower bandwidth for stable frequency maintenance. This segmentation allows each path to be optimized for its specific function, with the fast path handling acquisition and the slow path handling steady-state operation, thereby achieving both fast lock time and high stability.
2Loss of time
If the loop bandwidth is increased to speed up frequency acquisition, then the lock time is reduced, but the frequency control stability deteriorates
Solution Approach 1:
The system dynamically adjusts the effective loop bandwidth by switching between control paths. During frequency acquisition, the fast control path provides higher loop bandwidth for rapid response. After lock is achieved, the system switches to the slow control path which provides lower loop bandwidth for stable frequency control, thus adapting the bandwidth to the operational requirements.
Solution Approach 2:
The patent employs periodic switching between control modes: initially using the fast control path for acquisition, then transitioning to the slow control path for maintenance. This periodic action pattern allows the system to benefit from high bandwidth when needed and low bandwidth when stability is paramount.
Data Source
AI summary
A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.