Dual-PCB Fast-Charging Layout for Lower Loss and Heat
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Solution Overview
Problem
Electronic devices capable of fast charging face challenges such as increased size due to components handling high currents, higher DC resistance, and heat generation, which can reduce charging efficiency and hinder miniaturization.
Innovation Solution
The electronic device incorporates a dual PCB structure with separate charging ICs for normal and fast charging, allowing the processor to selectively activate the second charging IC for fast charging, thereby shortening the charging route and reducing power loss and heat generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single charging route is used for both normal and fast charging, then the device structure remains simple, but the charging efficiency decreases and heat generation increases during fast charging
Solution Approach 1:
The charging route is segmented into two independent paths: a normal charging route (first charging IC) and a fast charging route (second charging IC). Each route is optimized for its specific charging mode, allowing the fast charging route to use lower resistance components and direct battery connection, thereby improving charging efficiency while maintaining manageable device complexity through modular architecture.
2Productivity
If high current is applied for fast charging, then charging speed increases, but power loss and heat generation increase
Solution Approach 1:
The fast charging route implements local quality optimization by using low DC resistance components specifically in the high current path. The second charging IC and associated trace routing are designed with optimized conductivity for fast charging conditions, allowing high current to flow with minimal power loss and heat generation in the critical charging path.
3Productivity
If components handling high current are included for fast charging, then fast charging capability is achieved, but the device size increases
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) to accommodate fast charging components. The second charging IC is positioned on a PCB layer closer to the battery, and trace routing is optimized to minimize lateral expansion. This vertical arrangement allows high current handling components to be integrated without proportionally increasing the device's planar footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves charging efficiency, reduces heat generation, and facilitates miniaturization by individualizing the fast-charging route, enhancing both charging speed and device compactness.
Implementation Method 1
when a route for charging gets longer, a DC resistance (DCR) may get higher, and as high current flows during fast charging, power loss may occur
Implementation Method 2
as high current flows during fast charging, power loss may occur. In turn, heat may be generated in the electronic device
Data Source
AI summary
An electronic device capable of selectively performing normal charging and fast charging,, may comprise: a battery having a first surface and a second surface facing a different direction than the first surface, and includes a first connector and a second connector; a first printed circuit board (PCB) connected to the first connector and disposed closer to the first surface than to the second surface of the battery; a second PCB connected to the second connector and disposed closer to the second surface than to the first surface of the battery; a first charging integrated circuit (IC) and a second chargingIC configured to supply power to the battery; at least one processor, comprising processing circuitry, disposed at the first PCB and configured to select one of fast charging and normal charging of the battery based on a charging algorithm; and a charging port connected to the second PCB, wherein at least one processor, individually and/or collectively, is configured to turn off the second charging IC to perform normal charging of the battery and turn on the second charging IC to perform fast charging of the battery, and the second charging IC is disposed at the second PCB and is configured to supply power from the second PCB to the battery through the second connector.