Dual Phase Detector Clock Synchronization Without Harmonic Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase detection circuits in semiconductor apparatuses face challenges in accurately synchronizing clock signals, leading to issues such as harmonic locking, which affects the precision of clock signal phase adjustment and synchronization.
Innovation Solution
A phase detection circuit comprising a clock divider, unit delay, first and second phase detectors, and an initialization signal generator, which generates detection signals to adjust the delay amount of the output clock signal by comparing the phases of the reference and feedback clock signals, thereby preventing harmonic locking and ensuring precise synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional phase detection circuit is used to synchronize clock signals, then the circuit can operate with a simple structure, but harmonic locking occurs which degrades the precision of phase adjustment
Solution Approach 1:
The phase detection function is divided into two separate phase detectors: a first phase detector that compares the divided clock signal with a delayed version of the feedback clock signal, and a second phase detector that compares the divided clock signal with the feedback clock signal directly. This segmentation allows each detector to operate in different modes, preventing harmonic locking while maintaining synchronization reliability.
Solution Approach 2:
A delay element is introduced as an intermediary component between the feedback clock signal path and the first phase detector. This delay element adjusts the phase of the feedback clock signal to align with the divided clock signal, serving as a mediator that enables accurate phase comparison without causing harmonic locking.
2Measurement precision
If the phase detection circuit uses multiple phase detectors and delay elements to prevent harmonic locking, then phase adjustment precision is improved, but the circuit complexity increases
Solution Approach 1:
The divided clock signal generated by the clock divider serves multiple functions: it is used as the reference signal for both the first and second phase detectors, and it also serves as the input to the delay element. This multi-functionality reduces the need for additional signal generation circuits, thereby limiting the increase in circuit complexity despite the addition of multiple phase detectors.
3Loss of time
If the clock divider frequency is adjusted to improve phase synchronization, then the timing accuracy is improved, but the risk of harmonic locking increases
Solution Approach 1:
The feedback clock signal is fed back to both phase detectors, creating a feedback mechanism that continuously monitors and adjusts the phase relationship between the divided clock signal and the original clock signal. This feedback ensures that timing synchronization accuracy is maintained while the dual-phase-detector architecture prevents harmonic locking, thereby maintaining stability.
Data Source
AI summary
A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.