Dual-PLL Clock Generation for Jitter and Crosstalk Control
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Solution Overview
Problem
Crosstalk between adjacent clock signal generators in high-frequency applications above 10 GHz leads to spurious emissions, which are challenging to mitigate due to the need for narrow bandwidth Phase Locked Loops (PLLs) that compromise crosstalk immunity, especially when multiple Clock Multiplier Units (CMUs) are integrated on the same die or board.
Innovation Solution
The integration of multiple adjacent PLLs with wider bandwidth CMUs, where each CMU includes a further PLL, and a clock unit that performs integer or fractional frequency division and multiplication operations to generate clock signals with closely spaced frequencies, effectively reducing crosstalk by moving spurs outside the frequency band of interest.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If narrow bandwidth PLLs are used to filter fractional-N noise and spurs, then jitter performance is improved, but crosstalk immunity deteriorates
Solution Approach 1:
The system divides the PLL functionality into two separate segments: a first PLL (cleanup PLL) with narrow bandwidth dedicated to jitter filtering, and a second PLL (CMU PLL) with wider bandwidth dedicated to providing crosstalk immunity. This segmentation allows each PLL to be optimized for its specific function without compromise.
Solution Approach 2:
The invention introduces a new dimension to the architecture by adding a second PLL stage after the first PLL. This additional dimension allows the system to simultaneously achieve narrow bandwidth jitter filtering and wide bandwidth crosstalk rejection through cascaded PLL stages with different bandwidth characteristics.
2Device complexity
If multiple CMUs are integrated on the same die or board, then device complexity is reduced and space is saved, but crosstalk between adjacent generators increases
Solution Approach 1:
Each integrated CMU is divided into two functional segments: a first PLL for jitter cleaning and a second PLL for frequency multiplication with crosstalk immunity. This segmentation enables multiple CMUs to be tightly integrated while maintaining individual crosstalk isolation through the wider bandwidth second PLL stage.
Solution Approach 2:
The invention changes the bandwidth parameter of the second PLL to be wider than the first PLL, which fundamentally alters the frequency response characteristics and improves rejection of adjacent channel crosstalk while maintaining the benefits of integration.
3Object-affected harmful factors
If cleanup PLLs are displaced from each other to reduce crosstalk, then crosstalk immunity is improved, but device area increases and cost increases
Solution Approach 1:
The invention changes the bandwidth parameter of the second PLL to enable effective crosstalk rejection without requiring physical separation. The wider bandwidth second PLL acts as a filter that rejects adjacent channel interference, allowing tight integration while maintaining crosstalk immunity.
Solution Approach 2:
The system uses identical copies of the dual-PLL CMU architecture for multiple channels, where each copy is self-contained with its own first and second PLLs. This modular copying approach enables dense integration while maintaining performance through the inherent crosstalk rejection of the second PLL stage.
Data Source
AI summary
Integrated jitter compliant clock signal generation apparatus and methods are provided. Input signals having different frequencies are used to generate respective clock signals having closely spaced frequencies. The input signals might be generated, for example, in adjacent Phase Locked Loops (PLLs) which receive reference clock signals. The reference clock signals, or signals from which the reference clock signals originate, are also closely spaced. The closely spaced reference clock signals are effectively separated for cleanup and then brought back together to provide the closely spaced clock signals. This allows cleanup of the closely spaced reference clock signals to occur at staggered and more widely spaced frequencies. These techniques could also be applied to reference clock signals which are harmonically related and are used to generate harmonically related output clock signals.