Dual-PLL Clock Generation With Matched Delay for Jitter Reduction
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Solution Overview
Problem
Conventional clock generation systems face challenges in reducing both input and internal jitter simultaneously, leading to significant overall jitter that compromises system efficiency and performance, as they often require compromising on phase-locked loop (PLL) bandwidth to address one type of jitter while allowing the other to persist.
Innovation Solution
A clock system incorporating a low bandwidth PLL to filter input jitter and a high bandwidth PLL to filter internal jitter, with a matched delay path to minimize overall jitter, using a local feedback path to isolate the high bandwidth PLL from jitter sources and a programmable frequency multiplier to adjust clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a low bandwidth PLL is used to filter input jitter, then input jitter is reduced, but internal jitter is passed through
Solution Approach 1:
The system divides the clock generation function into two separate PLLs: a low bandwidth PLL for filtering input jitter and a high bandwidth PLL for filtering internal jitter. This segmentation allows each PLL to be optimized for its specific jitter filtering function without compromise
Solution Approach 2:
The low bandwidth PLL acts as an intermediary between the reference clock and the high bandwidth PLL. It pre-filters the input clock signal to remove input jitter before the signal enters the high bandwidth PLL, thereby protecting the high bandwidth PLL from amplifying input jitter while still allowing it to filter its own internal jitter
2Object-generated harmful factors
If a high bandwidth PLL is used to filter internal jitter, then internal jitter is reduced, but input jitter is passed through
Solution Approach 1:
The system assigns specific functions to each PLL based on their bandwidth characteristics. The high bandwidth PLL is dedicated to filtering internal jitter generated within itself, while the low bandwidth PLL handles input jitter filtering. This functional segmentation resolves the contradiction by ensuring each PLL operates in its optimal bandwidth regime
Solution Approach 2:
The low bandwidth PLL performs preliminary filtering of input jitter before the clock signal is processed by the high bandwidth PLL. This preliminary action prevents input jitter from being amplified by the high bandwidth PLL's internal noise multiplication, allowing the high bandwidth PLL to focus on filtering its own internal jitter
3Device complexity
If a single PLL bandwidth is used, then design is simplified, but both input and internal jitter cannot be reduced simultaneously
Solution Approach 1:
The system segments the jitter filtering function into two distinct PLLs with different bandwidths. This segmentation, while increasing component count, allows simultaneous optimization for both input jitter and internal jitter reduction, achieving overall jitter reduction that a single PLL cannot accomplish
Solution Approach 2:
The system changes the bandwidth parameter of the PLLs to create two distinct operational regimes. The low bandwidth PLL (e.g., 10-50 kHz) filters input jitter while the high bandwidth PLL (e.g., 1-10 MHz) filters internal jitter. This parameter differentiation enables simultaneous reduction of both jitter types
Data Source
AI summary
A clock system receiving a reference clock signal via an alignment location and developing a functional clock signal provided to a functional circuit via a clock path. The clock system includes a low bandwidth PLL, a high bandwidth PLL, and a delay path. The low bandwidth PLL receives the reference clock signal and a feedback clock signal and provides a filtered clock signal. The high bandwidth PLL receives the filtered clock signal and provides the functional clock signal, and has a feedback input coupled to its output via a local feedback path. The delay path is coupled between the output of the low bandwidth PLL and the alignment location to provide the feedback clock signal to the low bandwidth PLL. The delay and clock paths are substantially matched. The bandwidths of the low and high bandwidth PLLs may be individually configured to reduce both input jitter and internal jitter, respectively.