Dual Polarity Charge Pump for Flash Memory Soft Erase
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Solution Overview
Problem
Conventional flash memory cell erasure operations increase power consumption, reduce I/O transfer rates, and shorten the operational life due to the repetitive migration of charge across cell boundaries, limiting the number of erasure cycles before physical damage occurs.
Innovation Solution
Implementing a 'soft erase' operation that toggles an erasure status flag bit without physically migrating charge, allowing data to be overwritten based on status flag values, and using a dual polarity charge pump with positive and negative voltage sources to program memory cells, reducing the need for extensive charge migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory cell erasure operations are performed, then data can be cleared from memory cells, but power consumption increases and operational life decreases due to repetitive charge migration
Solution Approach 1:
The patent segments the erasure operation into two distinct modes: hard erasure for complete data clearing and soft erasure for incremental updates. This segmentation allows the system to choose the appropriate erasure method based on data management needs, reducing unnecessary charge migration and extending operational life while managing power consumption efficiently.
Solution Approach 2:
The patent inverts the conventional approach by introducing negative polarity programming that adds electrons to the floating gate, opposite to the traditional positive polarity that removes electrons. This inversion enables soft erasure operations that can update data without complete charge migration, thereby reducing wear and extending operational life.
2Productivity
If conventional hard erasure operations are performed frequently, then data can be updated, but I/O transfer rates decrease and operational life shortens
Solution Approach 1:
The patent implements dynamic erasure mode selection that adapts based on data update requirements. The system can switch between hard and soft erasure modes, allowing frequent data updates through soft erasure without the performance penalty and wear associated with hard erasure, thereby maintaining high I/O transfer rates while extending operational life.
Solution Approach 2:
The patent changes the electrical parameters of the erasure operation by introducing negative polarity voltage sources. This parameter change enables soft erasure operations that modify charge states without complete charge migration, reducing the wear impact of frequent updates while maintaining data accessibility and I/O performance.
3Ease of operation
If positive polarity voltage is applied to program memory cells, then data can be written, but the memory cells wear out faster due to charge migration
Solution Approach 1:
The patent introduces asymmetric polarity operation by implementing both positive and negative polarity programming modes. This asymmetry allows the system to use negative polarity for soft erasure and data updates, reducing the reliance on positive polarity operations that cause wear, thereby extending operational life while maintaining full programming capability.
Solution Approach 2:
The patent substitutes the traditional charge removal mechanism (positive polarity) with an alternative charge addition mechanism (negative polarity). This substitution enables data updates through electron injection rather than electron removal, reducing the wear associated with repeated positive polarity programming operations.
4Reliability
If soft erase operation is implemented using dual polarity charge pump, then charge migration is reduced and operational life is extended, but device complexity increases
Solution Approach 1:
The patent implements a dual polarity charge pump that serves multiple functions: positive polarity programming, negative polarity programming, soft erasure, and hard erasure. This multi-functionality justifies the increased device complexity by consolidating multiple operations into a single unified structure, reducing the need for separate circuits for each operation.
Solution Approach 2:
The patent merges the positive and negative polarity voltage generation circuits into a single integrated charge pump structure. This consolidation reduces the overall device complexity compared to having separate circuits for each polarity, while still enabling all necessary programming and erasure operations through the unified dual polarity system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, maintains higher I/O transfer rates, and extends the operational life of flash memory by minimizing wear and eliminating the need for frequent hard erasures, while allowing for efficient data management and storage.
Implementation Method 1
a positive polarity voltage source which applies a positive voltage to a charge storage device to program a selected memory cell to a first programming state
Implementation Method 2
a negative polarity voltage source which applies a negative voltage to the charge storage device to program the selected memory cell to a different, second programming state
Data Source
AI summary
Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In some embodiments, an apparatus includes an array of memory cells and a dual polarity charge pump. The dual polarity charge pump has a positive polarity voltage source which applies a positive voltage to a charge storage device to program a selected memory cell to a first programming state, and a negative polarity voltage source which applies a negative voltage to the charge storage device to program the selected memory cell to a different, second programming state.