Dual-Port Subthreshold SRAM Cell for Low-Power FIFO Systems
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Solution Overview
Problem
Conventional dual-port SRAMs face challenges in operating at subthreshold voltage due to diminished static noise margin (SNM) and increased power consumption, which affects their stability and suitability for long operations in nano-technology and biomedical electronic systems.
Innovation Solution
A dual-port subthreshold SRAM cell design that includes a write bit line, write word line, read bit line, read word line, a write access module, a latch with a pass transistor and cross-coupled inverters, and a read module, which enhances writing and reading capabilities by utilizing the reverse short-channel effect to reduce threshold voltage and eliminate positive feedback loops, thereby increasing SNM and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dual-port SRAM is used, then read and write operations can be performed, but static noise margin (SNM) becomes smaller and the device cannot operate at subthreshold region
Solution Approach 1:
The patent divides the SRAM cell into separate read and write paths with independent control. The read path uses read transistors connected to read bit lines, while the write path uses write transistors connected to write bit lines. This segmentation allows independent optimization of read and write operations, enabling stable subthreshold operation by preventing signal interference between read and write paths that would otherwise diminish SNM.
Solution Approach 2:
The patent introduces separate read and write bit lines as intermediary elements between the external circuit and the memory cell. These intermediary bit lines isolate the read and write operations, preventing direct signal conflict at the memory node. The read bit lines carry read signals without interfering with write operations, and vice versa, thereby maintaining adequate SNM for subthreshold operation.
2Reliability
If additional control circuits are added to enhance writing capability, then write margin is improved, but power consumption increases and chip area increases
Solution Approach 1:
The patent employs dynamic control of the write operation through word line activation. The write word line is activated only during write operations to enable the write transistors, and deactivated during read operations. This dynamic control provides adequate write margin when needed without requiring additional static control circuits that would increase power consumption and chip area during idle periods.
Solution Approach 2:
The patent changes the operational parameters of the write transistors by controlling their gate voltages through the write word line. During write operations, the write word line is raised to a voltage level that turns on the write transistors, enabling strong write capability. During read operations, the write word line is lowered to turn off the write transistors, eliminating the need for additional control circuits while maintaining write margin when required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-port subthreshold SRAM cell operates stably at subthreshold voltage with enhanced read and write capabilities, increased SNM, and reduced power consumption, making it suitable for FIFO memory systems and other applications requiring low power and long operation.
Implementation Method 1
utilizing the reverse short-channel effect to reduce threshold voltage and eliminate positive feedback loops
Data Source
AI summary
An innovative dual-port subthreshold static random access memory (SRAM) cell for sub-threshold voltage operation is disclosed. During write mode, the dual-port subthreshold SRAM cell would cut off the positive feedback loop of the inverters and utilize the reverse short-channel effect to enhance write capability. The single-ended read/write port structure further reduces power consumption of the lengthy bit line. Therefore, the dual-port subthreshold SRAM cell is a suitable for long operation in a first-in first-out memory system. Although the lower voltage reduces the stability of the memory cell, the dual-port subthreshold SRAM cell of the present invention can still stably operate.