Dual-Purpose JTAG Interconnects for Multi-IC Testing
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Solution Overview
Problem
In multiple-IC systems, such as system-in-package (SiP), there is often an insufficient number of available package pins to support dedicated external JTAG interface pins for each IC, leading to challenges in testing, as existing configurations require all ICs except the one under test to be set into a 'TDI-to-TDO bypass mode, which limits the ability to fully test internal ICs without direct JTAG connections and increases inter-IC routing.
Innovation Solution
The implementation of complementary test circuitry on multiple ICs, including dual-purpose interconnects that can function as both JTAG and slave/master ports, reduces the need for external JTAG pins and inter-IC routing by allowing internal ICs without direct JTAG connections to be fully testable, and enables multiplexing of JTAG interconnects with input slave and output master ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single set of external JTAG interface pins is used to connect to multiple ICs, then the number of package pins is reduced, but the ability to test internal ICs without direct JTAG connections is limited and inter-IC routing complexity increases
Solution Approach 1:
The patent implements dual-purpose interconnects that can function as either JTAG interface connections or slave/master port connections depending on the operational mode. This allows the same physical interconnect structure to serve multiple functions, reducing the total number of package pins required while maintaining full testing capability for all ICs in the system.
Solution Approach 2:
The patent divides the system into ICs with direct JTAG connections (master ICs) and ICs without direct JTAG connections (slave ICs). Each IC segment can operate independently in test mode, allowing comprehensive testing of the entire system while using a single set of external JTAG pins through coordinated bypass modes.
2Ease of operation
If all ICs except the one under test are set into TDI-to-TDO bypass mode, then access to the IC under test is enabled, but the testing capability for internal ICs is limited
Solution Approach 1:
The patent implements dynamic mode switching capability where ICs can transition between functional mode and JTAG test mode. This allows the system to adapt its configuration based on which IC is being tested, enabling any IC to be the active test target while others operate in bypass mode, thereby providing versatile testing capability for all internal ICs.
Solution Approach 2:
The patent introduces intermediary routing paths through master ICs that have direct JTAG connections. These master ICs act as mediators, allowing test signals to reach slave ICs without direct external JTAG pins. This intermediary approach enables comprehensive testing of all ICs while maintaining ease of operation through a unified external interface.
3Quantity of substance
If dual-purpose interconnects are implemented, then the need for external JTAG pins is reduced, but the complexity of managing multiple operational modes increases
Solution Approach 1:
The patent implements self-service mechanisms where each IC automatically manages its own operational mode based on system configuration signals. The ICs autonomously switch between functional mode and JTAG test mode without requiring complex external control, thereby reducing the overall system complexity despite the dual-purpose nature of the interconnects.
Data Source
AI summary
Embodiments include systems that include at least one integrated circuit (IC) and methods for their testing. Each IC includes an input interconnect to receive an input signal, a test enable interconnect to receive a test enable signal, and a controller (e.g., a TAP controller) for performing testing of the integrated circuit based on values in at least one register (values corresponding to the input signal). Each IC also includes an input port and a multiplexer coupled to the first input interconnect, the at least one register, and the input port. The multiplexer is controllable to pass the input signal to the input port in response to non-assertion of the test enable signal, and to pass the input signal to the at least one register in response to assertion of the test enable signal. When the system includes multiple controllers, each controller may implement a different opcode-to-instruction mapping.