Dual-Rail Logic Mapping for Faster Asynchronous Circuit Synthesis
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Solution Overview
Problem
The miniaturization of integrated circuits has led to stricter design and manufacturing specifications, requiring more complex and efficient electronic design automation (EDA) processes for logic synthesis, particularly in optimizing semiconductor device designs for performance, area cost, and power consumption, while ensuring that existing EDA tools struggle to effectively manage the complexity and variability in technology-dependent optimizations.
Innovation Solution
The implementation of a logic synthesis process that includes technology-independent logic optimization, technology mapping, performance analysis, and technology-dependent optimization, utilizing a cell library with dual-rail modules such as Pre-Charged Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB) modules, along with hybrid modules, to optimize circuit designs by selecting appropriate modules based on optimization objectives like timing, area, and power consumption, and considering satisfiability-don't-care conditions and NP-equivalence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If technology-dependent optimization is performed with multiple optimization objectives (timing, area, power), then design quality improves, but computation workload and processing time increase significantly
Solution Approach 1:
The optimization process is divided into separate independent optimization passes, each focused on a single objective (timing, area, or power). This segmentation allows each pass to be computationally efficient while the sequence of passes achieves multi-objective optimization, resolving the contradiction between comprehensive design quality and excessive processing time.
Solution Approach 2:
Technology-independent logic optimization is performed before technology mapping to simplify the logic network in advance. This preliminary action reduces the complexity of subsequent technology-dependent optimization passes, decreasing computation workload while maintaining the ability to achieve multiple optimization objectives.
2Adaptability or versatility
If existing EDA tools are used for logic synthesis, then basic functionality is maintained, but they struggle to manage the complexity and variability in technology-dependent optimizations
Solution Approach 1:
The system dynamically selects and configures optimization passes based on user-specified objectives and constraints. The optimization framework adapts to different design requirements by enabling or disabling specific passes (timing optimization, area optimization, power optimization) and adjusting parameters like effort levels and constraints, thereby managing optimization complexity while maintaining high adaptability.
Solution Approach 2:
Technology mapping serves as an intermediary step between logic optimization and implementation. It translates technology-independent optimized logic into technology-specific circuits using cell libraries, bridging the gap between abstract optimization and concrete implementation, which helps manage the complexity of technology-dependent optimizations.
3Area of moving object
If miniaturization is pursued to reduce device size, then area cost decreases, but design and manufacturing specifications become stricter
Solution Approach 1:
The optimization process adjusts multiple parameters (timing constraints, area constraints, power constraints, effort levels) to find the optimal balance for miniaturized designs. By dynamically changing these parameters based on manufacturing specifications and design goals, the system achieves area reduction while maintaining compliance with stricter design and manufacturing requirements.
Data Source
AI summary
A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.