Dual Rail Circuit Precharge Logic for SPA/DPA Attack Resistance
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Solution Overview
Problem
Circuits processing security-relevant data face challenges in preventing spurious impulses and undefined switching times due to transitions between calculation and precharge cycles, which can be exploited by attackers in SPA/DPA attacks, and existing dual rail circuit technologies are not synthesizable for static timing analyses.
Innovation Solution
A circuit and method that utilize a precharge circuit to ensure output changes only when all inputs have transitioned from the precharge cycle to the calculation cycle, and precharge values are output as soon as they are detected at any input, preventing premature output changes and spurious impulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a static implementation of dual rail circuitry with precharge signals is used, then the circuit can process security-relevant data, but spurious impulses occur during transitions between calculation and precharge cycles
Solution Approach 1:
The patent applies preliminary action by setting the output signal to the precharge state in advance when a precharge signal is detected at any input, before all inputs have completed their transition. This prevents spurious impulses by ensuring the output is already in the correct state when inputs transition, eliminating undefined switching times during cycle transitions.
2Reliability
If dynamic dual rail circuit technology is used to prevent spurious impulses, then security is improved, but the design and verification becomes time consuming and the circuit is not synthesizable
Solution Approach 1:
The patent changes the control parameter from dynamic timing-based control to static logic-based control using precharge signals. This allows the circuit to maintain security properties while being synthesizable and suitable for static timing analysis, as the output state is determined by logic conditions rather than dynamic timing sequences.
3Device complexity
If precharge values are passed through to the output during precharge cycles, then the circuit maintains simple logic, but undefined switching times occur during transitions
Solution Approach 1:
The patent uses feedback by continuously monitoring precharge signals at the inputs and using this information to control the output state. When a precharge signal is detected at any input, the output is set to the precharge state, creating a feedback mechanism that eliminates undefined switching times while maintaining simple circuit logic.
Data Source
AI summary
A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.


