Dual-Resonator Clock Oscillator for Multi-Frequency ICT Clocks
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Solution Overview
Problem
Existing clock oscillators cannot simultaneously meet the diverse requirements of different ICT application scenarios, leading to increased device complexity and production costs due to the need for multiple oscillators.
Innovation Solution
A clock oscillator is designed with a first resonator and a second resonator, along with a frequency synthesis module, where the output frequency of the first resonator is higher than the second resonator, generating a synthesis frequency that combines low-jitter and high-stability characteristics, allowing a single oscillator to meet multiple ICT clock application scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock oscillators are configured to meet different ICT application scenario requirements, then the requirements of different application scenarios are met, but device complexity and production costs increase
Solution Approach 1:
The patent implements a universal clock oscillator that can serve multiple ICT application scenarios through frequency synthesis. The oscillator uses a phase-locked loop (PLL) to synthesize multiple output frequencies from a single resonator, enabling one oscillator to replace multiple dedicated oscillators. This multi-functional design reduces device complexity and production costs while maintaining the ability to meet diverse frequency requirements across different application scenarios.
2Device complexity
If a single clock oscillator is used to meet multiple ICT application scenarios, then device complexity and production costs are reduced, but the ability to simultaneously meet different frequency requirements is compromised
Solution Approach 1:
The patent employs parameter changes through frequency synthesis to enable a single oscillator to provide multiple output frequencies. The phase-locked loop (PLL) circuit adjusts the output frequency parameter dynamically based on different application scenario requirements. By changing the frequency parameter while maintaining a single physical oscillator structure, the system achieves both cost reduction and frequency versatility.
3Ease of manufacture
If a single clock oscillator is used to meet multiple ICT application scenarios, then production costs are reduced, but the clock signal quality for different scenarios cannot be optimized
Solution Approach 1:
The patent segments the clock signal generation function into multiple independent output channels, each capable of providing optimized clock signals for different application scenarios. The frequency synthesis module divides the single resonator's output into multiple frequency channels through the PLL circuit, allowing each channel to be independently optimized for its specific application while sharing the same resonator, thus reducing production costs without compromising signal quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces device complexity and production costs by enabling a single clock oscillator to meet various ICT requirements, providing both low-jitter and high-stability clock signals.
Implementation Method 1
Frequency selection is implemented by using a resonance characteristic of the electrical/mechanical resonator, to generate a frequency signal that periodically oscillates
Implementation Method 2
the frequency synthesis module is configured to generate a synthesis frequency based on the output frequency of the first resonator and the output frequency of the second resonator
Data Source
Figure 1
Figure 2
Figure 3a~4
AI summary
A clock oscillator, a method for preparing the clock oscillator, a method for using the clock oscillator, and a chip that includes the clock oscillator are provided. The clock oscillator includes a first resonator, a second resonator, and a frequency synthesis module, where an output frequency of the first resonator is higher than an output frequency of the second resonator, the frequency synthesis module is configured to generate a synthesis frequency based on the output frequency of the first resonator and the output frequency of the second resonator, and the synthesis frequency is used as a clock frequency output by the clock oscillator. The clock oscillator uses both of the two resonators with the different output frequencies as clock signal sources, and generates a synthesized clock signal by using the frequency synthesis module. In this way, one clock oscillator is used to meet requirements of a plurality of ICT clock application scenarios, thereby reducing device complexity and production costs.