Dual Seal Ring Structure for Semiconductor Chip Area Reduction
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Solution Overview
Problem
The challenge is to minimize chip area occupation by seal rings in semiconductor devices while preventing cracks during dicing and protecting lower layers from etching damage, as excessive seal ring regions can lead to yield loss and internal circuit damage.
Innovation Solution
A method involving the formation of a first and second seal ring separated by a protective layer with a concave surface, where the protective layer is partially removed to create a spacer on the first seal ring's sidewall, reducing the seal ring width and improving step coverage, thereby minimizing chip area usage and preventing crack-related damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If seal rings are formed around a chip to prevent cracks during dicing, then crack prevention is improved, but chip area occupied by seal rings increases
Solution Approach 1:
The seal ring structure is divided into two separate seal rings instead of one continuous seal ring. This segmentation allows the seal rings to be positioned more efficiently, providing crack prevention functionality while reducing the total area occupied by the seal ring structure.
Solution Approach 2:
The protective layer is designed with different thicknesses in different regions - thicker at the bottom of the concave surface for etching protection, and thinner at the top to reduce overall area occupation. This local variation in quality optimizes both protection and area efficiency.
2Reliability
If protective layer thickness is increased to protect lower layers from etching damage, then protection capability is improved, but chip area and process complexity increase
Solution Approach 1:
The protective layer incorporates a concave surface (curved geometry) instead of a flat structure. This curvature allows the protective layer to provide enhanced etching protection at the bottom while maintaining a compact overall profile, reducing the need for additional protective structures.
Data Source
AI summary
Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.