Memory Cells With Dual Select Transistors For Voltage Stress Reduction
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Solution Overview
Problem
Existing memory technologies face challenges in reducing punch-through voltage and electrode-to-electrode current voltage across select transistors during memory operations, which can lead to damage and inefficiencies in writing and reading data.
Innovation Solution
The implementation of memory cells with two select transistors per cell, each coupled to two different word lines controlled by separate addressable word line drivers, allowing for the application of different voltages to reduce punch-through voltage and current across select transistors during memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single select transistor is used per memory cell, then the device complexity is reduced, but the voltage stress across the transistor increases causing punch-through and damage
Solution Approach 1:
The single select transistor function is segmented into two separate select transistors, each controlled by a different word line. This segmentation divides the voltage stress burden, allowing each transistor to operate at lower voltages and reducing punch-through effects while maintaining the memory cell's select functionality.
2Productivity
If higher voltages are applied across select transistors to improve write capability, then the write efficiency is improved, but the transistor damage and punch-through increase
Solution Approach 1:
The voltage application path is segmented into two word lines, each controlling a separate select transistor. This allows the total voltage required for write operations to be distributed across two transistors, reducing the voltage stress on each individual transistor and preventing punch-through while maintaining effective write capability.
Solution Approach 2:
The second select transistor and its associated word line act as an intermediary element that distributes and controls voltage application to the memory cell. This intermediary structure enables voltage management that prevents harmful punch-through effects while achieving the necessary write efficiency.
3Reliability
If different voltages are applied to word lines to reduce punch-through, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The word line control function is segmented into multiple independent word line driver circuits, each managing a specific word line. This segmentation allows each driver to be optimized for specific voltage requirements, improving reliability through better voltage management while keeping each individual driver circuit relatively simple.
Data Source
AI summary
A memory includes memory cells having two select transistors per cell. Each of the two select transistors are coupled to two different word lines with each word line being controlled by a separate addressable word line driver circuit. In some embodiments, providing two different word lines from two different word line drivers may provide for a memory where the word lines can apply different voltages based on the memory operation being performed.