Dual-Side Cooling for Packaged Electronic Devices
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Solution Overview
Problem
Lateral field effect transistors (FETs) in packaged electronic devices face challenges in heat dissipation due to limited thermal capacity of bond pad layouts and the poor thermal conductivity of electrically isolating thermal interface materials, which hinders increased power density and energy efficiency, especially in wide-band-gap transistors like GaN power stage FETs.
Innovation Solution
A packaged electronic device design that includes a die attach pad with semiconductor dies attached to both sides, a multi-layer substrate with ceramic and metal layers for enhanced thermal paths, and a package structure that exposes metal layers for both topside and bottom-side heat removal, allowing for improved thermal management through dual-side cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If heat is dissipated through the bottom side of the die and package using a die attach pad, then thermal management is improved, but the thermal capacity is limited by the bond pad layout and poor thermal conductivity of electrically isolating materials
Solution Approach 1:
The patent transitions from single-sided bottom cooling to dual-sided cooling by exposing thermal paths on both the bottom side (die attach pad) and top side (metal layer of substrate) of the package, effectively adding a dimensional aspect to heat dissipation
Solution Approach 2:
The thermal management system is segmented into two independent cooling paths: one through the bottom die attach pad and another through the top metal layer, allowing each path to be optimized independently and increasing overall thermal capacity
2Reliability
If electrically isolating thermal interface material is used between the heatsink and PCB, then electrical isolation is achieved, but thermal conductivity deteriorates
Solution Approach 1:
The patent extracts the electrical isolation function from the thermal interface material by implementing it through the substrate structure itself (via the isolator layer between metal layers), allowing the use of highly conductive thermal materials without electrical isolation compromises
3Productivity
If power density is increased in WBG transistors, then energy efficiency is enhanced, but heat dissipation becomes more difficult due to limited thermal capacity
Solution Approach 1:
The patent adds a top-side thermal path dimension to complement the traditional bottom-side cooling, providing an additional degree of freedom for heat removal that scales with increasing power density
Solution Approach 2:
The substrate employs a composite structure with high thermal conductivity materials (metal layers, ceramic) specifically selected and arranged to maximize heat dissipation capability while supporting high power density operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design facilitates efficient heat removal from both sides of the device, reducing transistor junction temperature, enhancing reliability, and increasing power density by dividing thermal resistance into parallel paths, thus supporting high-power applications.
Implementation Method 1
Heat generated from the die dissipates through a bottom side substrate to the outside of the package
Implementation Method 2
The design facilitates efficient heat removal from both sides of the device, reducing transistor junction temperature
Data Source
AI summary
A packaged electronic device includes a package structure that encloses first and second semiconductor dies, a die attach pad with a first side attached to one of the dies, and a second side exposed along a side of the package structure, and a substrate that includes a first metal layer exposed along another side of the package structure, a second metal layer soldered to contacts of the dies, and an isolator layer that extends between and separates the first and second metal layers.