Dual-Side MRAM Access Circuits for Programming Voltage Drop
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Solution Overview
Problem
Existing MRAM devices face voltage drop issues due to increased resistance in metal lines as technology nodes shrink, leading to insufficient programming voltage for MRAM cells far from driver and pull-down circuits, especially in large memory arrays.
Innovation Solution
Implementing driver and pull-down circuits on opposite sides of the memory array, with multiple sub-circuits on each side to reduce equivalent resistance and enhance programming voltage delivery to each MRAM cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If driver and pull-down circuits are placed on the same side of the memory array, then device complexity is reduced, but voltage drop increases due to longer conduction paths
Solution Approach 1:
The patent divides the access circuits into multiple segments positioned at different locations around the memory array. Specifically, driver circuits and pull-down circuits are distributed to opposite sides of the array, creating multiple access paths that segment the current flow and reduce the effective conduction distance for any given memory cell.
Solution Approach 2:
The patent transitions from a one-sided circuit arrangement to a two-sided or multi-sided arrangement around the memory array. By positioning access circuits on opposite sides or at multiple corners of the array, the invention adds spatial dimensionality to the circuit layout, enabling shorter conduction paths in multiple directions.
2Area of stationary object
If access circuits are positioned far from memory cells, then area utilization improves, but resistance in metal lines increases
Solution Approach 1:
The patent implements local quality by positioning access circuits specifically at opposite sides or corners of the memory array, creating localized access regions. This strategic placement ensures that each memory cell has nearby access circuits in at least one direction, reducing local resistance while maintaining overall area utilization.
3Productivity
If minimum feature size is reduced to increase integration density, then productivity improves, but metal line resistance increases
Solution Approach 1:
By segmenting the access circuits and distributing them around the memory array, the patent reduces the maximum distance any signal must travel through metal lines. This segmentation compensates for the increased resistance inherent in smaller feature sizes by shortening the conduction paths.
Solution Approach 2:
The multi-sided circuit arrangement adds dimensional diversity to the layout, allowing signals to travel in multiple directions rather than being constrained to single long paths. This dimensional approach reduces the effective resistance even as feature sizes shrink.
Data Source
AI summary
A memory circuit includes a memory array comprising a plurality of non-volatile memory cells, wherein the non-volatile memory cells are arranged along a plurality of access lines that extend along a lateral direction. The memory circuit includes a first access circuit physically disposed on a first side of the memory array in the lateral direction. The memory circuit includes a second access circuit physically disposed on a second side of the memory array in the lateral direction, the second side being opposite to the first side. When each of the non-volatile memory cells is configured to be programmed by at least a first current and a second current, the first current and second current flow through a first path and a second path, respectively. The first path at least comprises a portion on the first side and the second path at least comprises a portion on the second side.